In partially run-time reconfigurable (PRR) FPGAs, hardware tasks should be configured before their execution. The configuration delay imposed by the reconfiguration process increases the total execution time of the hardware tasks and task graphs. In this paper, a new technique named forefront - fetch is presented to improve the makespan of hardware task graphs running on PRR FPGAs via alleviating the adverse effects of the configuration delays. In this technique, which is applied to a sequence of task graphs, the configuration of some tasks is carried out within the execution phase of the previous task graph. This strategy leads to hide the configuration delay of the forefront-fetched tasks that as a result improves the execution time. The proposed solution modifies the schedules of the task graphs at design time to obtain a set of schedule pairs for the run-time environment. Experiments on actual and synthesized task graphs demonstrate the ability of the proposed technique in improving the makespan of hardware task graphs. The obtained results show that for a set of task graphs running on Xilinx™ Virtex-5 XUPV5LX110T FPGA, makespan is improved by 37.81% on average. Moreover, the proposed solution outperforms state-of-the-art prefetch-aware scheduling strategies by 14.78% makespan improvement.

中文翻译：

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基于 FPGA 的多任务图系统的预取感知调度

在部分运行时可重配置 (PRR) FPGA 中，硬件任务应在执行之前进行配置。重新配置过程造成的配置延迟增加了硬件任务和任务图的总执行时间。在本文中，提出了一种名为最前沿 - 提取的新技术，通过减轻配置延迟的不利影响来提高运行在 PRR FPGA 上的硬件任务图的完工时间。在这种应用于任务图序列的技术中，一些任务的配置是在前一个任务图的执行阶段进行的。这种策略导致隐藏最前沿提取任务的配置延迟，从而提高了执行时间。所提出的解决方案在设计时修改任务图的调度以获得运行时环境的一组调度对。实际和合成任务图的实验证明了所提出的技术在提高硬件任务图的完工时间方面的能力。获得的结果表明，对于在 Xilinx™ Virtex-5 XUPV5LX110T FPGA 上运行的一组任务图，makespan 平均提高了 37.81%。此外，所提出的解决方案比最先进的预取感知调度策略提高了 14.78% 的完工时间。makespan 平均提高了 37.81%。此外，所提出的解决方案比最先进的预取感知调度策略提高了 14.78% 的完工时间。makespan 平均提高了 37.81%。此外，所提出的解决方案比最先进的预取感知调度策略提高了 14.78% 的完工时间。