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Three-dimensional mechanistic modeling of gate leakage current in high-κMOSFETs
Physical Review Applied ( IF 3.8 ) Pub Date : 
Feilong Liu, Yue-Yang Liu, Ling Li, Guofu Zhou, Xiangwei Jiang, and Jun-Wei Luo

Gate leakage current is a crucial issue for the reliability of modern high-κ MOSFETs. Although various physical models describing both direct tunneling and trap-assisted contribution of leakage current have been presented in literature, many of them treats traps in the dielectric as a continuum distribution in energy and position, and trap-to-trap transport of electrons has so far been mostly neglected or not treated three-dimensionally (3D). In this work, we present a mechanistic model for calculation of gate leakage current in high-κ MOSFET multi-layer stacks based on multi-phonon trap-assisted tunneling theory, taking into account the intrinsic 3D discreteness of traps in the dielectric. Our model can to a good approximation reproduce the experimental results at different dielectric thicknesses, gate voltages, temperatures, and different gate materials. We find that in realistic devices, the 3D trap-to-trap transport of electrons contributes a non-negligible part to the gate leakage current. This contribution is more pronounced at low-voltage device operations, which is important for low-power applications. We calculate the intrinsic fluctuation of gate leakage current due to positional and energetic disorder of traps in the dielectric, and conclude that positional disorder is more important than energetic disorder for realistic material parameters. The calculated gate leakage current depends sensitively on temperature, trap energy, and trap density. We provide a computationally efficient 3D master equation approach that enables 3D mechanistic simulation of 103 traps on the order of minutes on a standard desktop computer.

中文翻译:

高κMOSFET中栅极泄漏电流的三维力学建模

栅极漏电流对于现代高可靠性的可靠性至关重要。κMOSFET。尽管文献中已经描述了各种物理模型,它们描述了直接隧穿和陷阱辅助的泄漏电流的贡献,但许多模型将电介质中的陷阱视为能量和位置的连续分布,电子的陷阱到陷阱传输已经如此。远远没有被忽略或没有进行三维处理(3D)。在这项工作中,我们提出了一种用于计算高电流下栅极漏电流的机制模型。κ基于多声子陷阱辅助隧穿理论的MOSFET多层堆栈,考虑了电介质中陷阱的固有3D离散性。我们的模型可以很好地重现不同介电层厚度,栅极电压,温度和不同栅极材料下的实验结果。我们发现,在实际的设备中,电子的3D陷阱到陷阱传输对栅极泄漏电流的贡献不可忽略。这种贡献在低压设备操作中更为明显,这对于低功耗应用很重要。我们计算了由于电介质中陷阱的位置和能量紊乱引起的栅极泄漏电流的内在波动,并得出结论:对于实际的材料参数,位置紊乱比能量紊乱更为重要。计算得出的栅极泄漏电流敏感地取决于温度,陷阱能量和陷阱密度。我们提供了一种计算效率高的3D主方程方法,可对3D机械模型进行仿真103 在一台标准台式计算机上的陷阱数分钟。
更新日期:2020-01-13
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