A wideband 65-nm CMOS power amplifier (PA) is presented, with a decade frequency range from 600 MHz to 6.0 GHz. In this frequency range, the output power exceeds 26.6 dBm and the power gain and power-added efficiency (PAE) exceed 18.1 dB and 49%, respectively. For a 7.5-dB peak-to-average-power-ratio (PAPR) long term evolution (LTE) signal at 1.9 GHz, the circuit provides an average output power of 19 dBm, with a PAE of 40%, and an adjacent channel leakage ratio (ACLR) exceeding −31 dBc. In LTE measurements at 5.9 GHz, the average output power, PAE, and ACLR are 18.5 dBm, 38.8%, and −30 dBc, respectively, using supply modulation and baseband predistortion. The wide bandwidth (BW) and high performance are achieved by introducing a dual output topology with an off-chip higher order output-matching network, combined with a positive feedback cross-coupled differential cascode amplifier stage. By using supply modulation and dynamic gate bias with an injection-locked PA, improved back-off efficiency, and acceptable out-of-band and in-band distortion is obtained. The integrated circuit occupies an area of 1.0 $\times $ 0.73 mm2 in standard 65-nm CMOS technology and uses a supply of 3.0 V.

中文翻译：

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用于低于 6GHz 蜂窝终端的 10 倍频范围 CMOS 功率放大器

展示了宽带 65-nm CMOS 功率放大器 (PA)，频率范围为 600 MHz 至 6.0 GHz。在该频率范围内，输出功率超过 26.6 dBm，功率增益和功率附加效率 (PAE) 分别超过 18.1 dB 和 49%。对于 1.9 GHz 的 7.5 dB 峰均功率比 (PAPR) 长期演进 (LTE) 信号，该电路可提供 19 dBm 的平均输出功率，PAE 为 40%，以及相邻信道泄漏比 (ACLR) 超过 -31 dBc。在 5.9 GHz 的 LTE 测量中，使用电源调制和基带预失真的平均输出功率、PAE 和 ACLR 分别为 18.5 dBm、38.8% 和 -30 dBc。通过引入带有片外高阶输出匹配网络的双输出拓扑，实现了宽带宽 (BW) 和高性能，结合正反馈交叉耦合差分共源共栅放大器级。通过使用带有注入锁定 PA 的电源调制和动态栅极偏置，可以提高回退效率，并获得可接受的带外和带内失真。该集成电路采用标准 65 纳米 CMOS 技术占用 1.0 美元\乘以 0.73 平方毫米的面积，并使用 3.0 V 电源。