Abstract

An analog-to-digital converter based on the time-interleaved delta-sigma modulator is a proper method for high-speed ADCs. Time-interleaved delta-sigma modulators (TIDSM) can be successfully implemented with the development of the block digital filtering (BDF) technique. In this method, M mutually cross-connection delta-sigma modulators are used, with each one operating at a sampling rate of \({\text{f}}_{\text{s}}\) hence, the effective sampling rate will be \({\text{M}}*{\text{f}}_{\text{s}}\) However, SNDR is approximately equal to the single path standard structure. In this paper, a new structure based on the Noise Coupled time-interleaved delta-sigma modulator is proposed to increase the overall noise transfer function order without any additional active element. This improvement is analytically verified and then validated using simulations. Also, some practical issues regarding the implementation of the proposed structure, such as, finite op-amp’s gain and mismatching effects are discussed. Also, analyzes and some practical solutions are presented. The results of the simulation at the system level show that the SNDR of the proposed first-order two-channel structure is 18 dB better than its BDF technique counterpart, for the second-order two-channel TIDSM, the SNDR of the proposed structure is 13 dB better than that of the BDF technique.

中文翻译：

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一种新颖的噪声耦合时间交织Δ-Σ调制器，具有实际局限性分析

摘要

基于时间交错的delta-sigma调制器的模数转换器是高速ADC的正确方法。随着块数字滤波（BDF）技术的发展，时间交错的delta-sigma调制器（TIDSM）可以成功实现。在这种方法中，使用了M个相互交叉连接的delta-sigma调制器，每个调制器都以\（{\ text {f}} _ {\ text {s}} \\}的采样率运行，因此，有效采样率将为\（{\ text {M}} * {\ text {f}} _ {\ text {s}} \\）但是，SNDR大约等于单路径标准结构。本文提出了一种基于噪声耦合时间交织Δ-Σ调制器的新结构，以在不增加任何有源元件的情况下提高整体噪声传递函数阶数。对此改进进行了分析验证，然后使用仿真进行了验证。此外，还讨论了有关所提出结构实现的一些实际问题，例如，有限运放的增益和失配效应。此外，提出了分析和一些实际的解决方案。在系统级的仿真结果表明，对于二阶双通道TIDSM，所提出的一阶双通道结构的SNDR比其BDF技术对应的SNDR好18 dB，