A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 \(\upmu \hbox {m}\) CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from 8 to 18 GHz. The fabricated chip occupies an area of \(1.2\times 2.7\) mm\(^{2}\) and has no DC power consumption.

中文翻译：

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用于X-Ku频段应用的CMOS集成延迟链

宽带集成延迟链芯片用5比特延迟控制，120个PS和PS 3.9延迟分辨率的最大延迟，设计并制造的0.18  \（\ upmu \ hbox中{M} \） CMOS技术被呈现。二阶全通网络（APN）在此延迟电路中用作延迟结构。在所制造芯片的两个MSB位的设计中，使用了一种新的设计方法，该方法允许使用更少数量的无源二阶APN电路来实现更高的群延迟。反过来，这将减少设计的延迟控制链的插入损耗。所制造的延迟链的测量结果显示，在8至18 GHz的预定频段上，插入损耗为12.6–20.5 dB，RMS延迟误差小于3.3 ps。制成的芯片占\（1.2 \乘以2.7 \） mm的面积\（^ {2} \）并且没有直流功耗。