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A peak efficiency tracking technique to improve the efficiency of switched capacitor DC–DC converters
Analog Integrated Circuits and Signal Processing ( IF 1.2 ) Pub Date : 2019-07-26 , DOI: 10.1007/s10470-019-01499-7
Stefano D’Amico , Carlo Veri , Giuseppe Tau , Mirko Pasca

In this paper, a peak efficiency tracking technique to improve the efficiency of switched capacitor (SC) DC–DC converters as the load varies is presented. A peak efficiency tracking circuit based on feedback control over the switching frequency is implemented for this scope. The basic idea of the proposed technique is to adjust the switching frequency according to the load. The technique is successfully implemented in a SC DC–DC converter to be embedded in detector pixels for the Large Hadron Collider (LHC) experiment at the Conseil Européen pour la Recherche Nucléaire (CERN) of Geneve. It is realized in 65 nm bulk CMOS technology with an occupied area of 1.31 mm2. This converter provides an 800 mV output voltage from a 1.2 V supply. The load of the DC–DC converters is modeled as a resistor, RLOAD, that has 4 Ω nominal value but it can range from 2.67 up to 10 Ω. At 10 Ω RLOAD, a 6% efficiency improvement is reached with respect to the typical approach consisting in keeping constant the switching frequency at the optimum value for RLOAD nominal value.

中文翻译:

一种峰值效率跟踪技术,可提高开关电容器DC-DC转换器的效率

在本文中,提出了一种峰值效率跟踪技术,以随着负载的变化提高开关电容器(SC)DC-DC转换器的效率。为此,实现了基于对开关频率的反馈控制的峰值效率跟踪电路。所提出技术的基本思想是根据负载调整开关频率。这项技术已成功实现在SC DC-DC转换器中,并嵌入到探测器的像素中,以用于日内瓦大学欧洲核子研究中心(CERN)的大型强子对撞机(LHC)实验。它采用65 nm体CMOS技术实现,占用面积为1.31 mm 2。该转换器从1.2 V电源提供800 mV输出电压。DC-DC转换器的负载建模为电阻RLOAD的标称值为4,但范围为2.67至10。在10Ω - [R LOAD,则到达相对于由在为最佳值保持恒定的开关频率的典型的方法有6%的效率改进- [R LOAD的标称值。
更新日期:2020-01-04
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