Emerging non-volatile memories (NVMs) have favorable properties, such as low leakage and high density, and have attracted a lot of attention in recent years. Among them, spin-transfer torque magnetoresistive random access memory (STT-MRAM) with SRAM-comparable read speed is a good candidate to build large last-level caches (LLCs). However, STT-MRAM suffers from long write latency and high write energy. To mitigate the impact of asymmetric read/write energy and latency, hybrid cache designs have been proposed to combine the merits of STT-MRAM and SRAM. In such a hybrid SRAM/STT-MRAM LLC, intelligent block placement and migration policies are needed to improve the energy efficiency. Prior studies map write-intensive blocks to SRAM and keep read-intensive blocks in STT-MRAM for reducing the energy consumption of hybrid LLCs. The write-intensive/read-intensive blocks are usually captured by sampling the address (PC) of memory access instructions or adding simple access counters in each cache line. Nevertheless, these prior approaches cannot fully capture the energy-harmful access behavior in STT-MRAM, especially the writes caused by repetitive data transfer between the LLC and upper-level caches. In this paper, we find that conflict misses in L2 often generate thrashing blocks which move back and forth between L2 and LLC. If dirty thrashing blocks that incur extensive writes are placed in STT-MRAM, energy consumption would excessively increase, especially when running memory-bound workloads. Thus, we propose a thrashing aware placement and migration policy (TAP) to tackle the challenge. TAP places dirty thrashing blocks into SRAM and migrates clean thrashing blocks from SRAM to STT-MRAM. Evaluation results show that TAP can provide significant energy savings with minimal performance loss.

中文翻译：

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TAP：通过 Thrashing Aware Placement 和 Migration 降低非对称混合最后一级缓存的能量

新兴的非易失性存储器 (NVM) 具有低泄漏和高密度等优点，近年来受到了广泛关注。其中，具有与 SRAM 相当的读取速度的自旋转移矩磁阻随机存取存储器 (STT-MRAM) 是构建大型末级缓存 (LLC) 的理想选择。然而，STT-MRAM 存在写入延迟长和写入能量高的问题。为了减轻非对称读/写能量和延迟的影响，已经提出混合缓存设计以结合 STT-MRAM 和 SRAM 的优点。在这种混合 SRAM/STT-MRAM LLC 中，需要智能块放置和迁移策略来提高能效。先前的研究将写入密集型块映射到 SRAM，并将读取密集型块保留在 STT-MRAM 中，以降低混合 LLC 的能耗。写密集型/读密集型块通常通过对内存访问指令的地址（PC）进行采样或在每个缓存行中添加简单的访问计数器来捕获。然而，这些先前的方法不能完全捕获 STT-MRAM 中的能量有害访问行为，尤其是由 LLC 和上层缓存之间的重复数据传输引起的写入。在本文中，我们发现 L2 中的冲突未命中通常会产生在 L2 和 LLC 之间来回移动的颠簸块。如果将导致大量写入的脏抖动块放置在 STT-MRAM 中，则能耗将过度增加，尤其是在运行受内存限制的工作负载时。因此，我们提出了一个有意识的安置和迁移政策 (TAP) 来应对这一挑战。TAP 将脏的抖动块放入 SRAM，并将干净的抖动块从 SRAM 迁移到 STT-MRAM。评估结果表明，TAP 可以以最小的性能损失提供显着的节能效果。