As DRAM scaling becomes ever more difficult, Phase Change Memory (PCM) is attracting attention as a new memory or storage class memory. Unfortunately, PCM cell data can be changed by frequently writing ‘0’ to adjacent cells. This phenomenon is called Write Disturbance (WD). To mitigate WD errors with low performance overhead, we propose a Detection Cell PCM (DC-PCM). In the DC-PCM, additional cells called Detection Cells (DC) are allocated to a memory-line to pre-detect WD errors. For pre-detection, we propose schemes that give DCs higher WD-vulnerability than normal cells. However, additional time is needed to verify DCs. To hide the time needed to perform the verifications during a WRITE, DC-PCM enables the local word-lines of DCs to operate independently (Decoupled Word-line), and verifies different directions in parallel (Parallel DC-Verification). After verification, the DC-PCM increases the WD-vulnerability of the DCs, or restores the memory-line data (DC-Correction). In our simulation, DC-PCMs showed performance comparable to a WD-free PCM for all workloads.

中文翻译：

---

DC-PCM：通过使用检测单元以低性能开销减轻 PCM 写入干扰

随着 DRAM 扩展变得越来越困难，相变存储器 (PCM) 作为一种新的存储器或存储类存储器正在引起人们的注意。不幸的是，PCM 单元数据可以通过频繁地向相邻单元写入“0”而改变。这种现象称为写干扰 (WD)。为了以低性能开销减轻 WD 错误，我们提出了检测单元 PCM (DC-PCM)。在 DC-PCM 中，称为检测单元 (DC) 的附加单元被分配给存储线以预检测 WD 错误。对于预检测，我们提出了使 DC 比正常细胞具有更高 WD 脆弱性的方案。但是，需要额外的时间来验证 DC。为了隐藏在写入期间执行验证所需的时间，DC-PCM 使 DC 的本地字线能够独立运行（解耦字线），并并行验证不同方向（Parallel DC-Verification）。验证后，DC-PCM 增加 DC 的 WD-脆弱性，或恢复内存线数据（DC-Correction）。在我们的模拟中，对于所有工作负载，DC-PCM 表现出与无 WD PCM 相当的性能。