Probabilistic machine learning enabled by the Bayesian formulation has recently gained significant attention in the domain of automated reasoning and decision-making. While impressive strides have been made recently to scale up the performance of deep Bayesian neural networks, they have been primarily standalone software efforts without any regard to the underlying hardware implementation. In this paper, we propose an "All-Spin" Bayesian Neural Network where the underlying spintronic hardware provides a better match to the Bayesian computing models. To the best of our knowledge, this is the first exploration of a Bayesian neural hardware accelerator enabled by emerging post-CMOS technologies. We develop an experimentally calibrated device-circuit-algorithm co-simulation framework and demonstrate $24\times$ reduction in energy consumption against an iso-network CMOS baseline implementation.

中文翻译：

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全自旋贝叶斯神经网络

由贝叶斯公式实现的概率机器学习最近在自动推理和决策领域获得了极大的关注。虽然最近在扩展深度贝叶斯神经网络的性能方面取得了令人印象深刻的进步，但它们主要是独立的软件工作，不考虑底层硬件实现。在本文中，我们提出了一种“全自旋”贝叶斯神经网络，其中底层的自旋电子硬件可以更好地匹配贝叶斯计算模型。据我们所知，这是对新兴后 CMOS 技术支持的贝叶斯神经硬件加速器的首次探索。