Monolithic three-dimensional (M3D) integration is viewed as a promising improvement over through-silicon-via-based 3-D integration due to its greater inter-tier connectivity, higher circuit density, and lower parasitic capacitance. With M3D integration, network-on-chip (NoC) communication fabric can benefit from reduced link distances and improved intra-router efficiency. However, the sequential fabrication methods utilized for M3D integration impose unique interconnect requirements for each of the possible partitioning schemes at transistor, gate, and block granularities. Further, increased cell density introduces contention of available routing resources. Prior work on M3D NoCs has focused on the benefits of reduced distances, but has not considered these process-imposed circuit complications. In this article, NoC topology decisions are analyzed in conjunction with these M3D interconnect requirements to provide an equivalent architectural comparison between M3D partitioning schemes.

中文翻译：

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单片 3D 集成的片上网络设计指南

由于具有更大的层间连接性、更高的电路密度和更低的寄生电容，单片 3D (M3D) 集成被视为对基于硅通孔的 3-D 集成的有希望的改进。通过 M3D 集成，片上网络 (NoC) 通信结构可以受益于缩短的链路距离和提高的路由器内效率。然而，用于 M3D 集成的顺序制造方法对晶体管、栅极和块粒度的每个可能的分区方案提出了独特的互连要求。此外，增加的单元密度会引起可用路由资源的竞争。之前关于 M3D NoC 的工作集中在减少距离的好处上，但没有考虑这些过程强加的电路复杂性。在本文中，