This letter presents two highly efficient two-stage power amplifiers (PAs) for 5G applications, implemented in a 22-nm slilicon on insulator (SOI) CMOS technology. High efficiency is achieved by carefully designing the power cells and optimizing the layout. Capacitive neutralization is used to improve the stability and the gain. Both PAs are similar except for the use of nMOS neutralization capacitors in the first one. In the second PA, we propose the use of pMOS capacitors instead to enhance significantly both stability and AM–PM linearity at the same time. For both PAs, the saturated output power is 12.7 dBm and $\text{P}_{\mathrm {1\,dB}}$ is 11.9 dBm from a 0.9-V supply at 33 GHz with a power-added efficiency (PAE) at $\text{P}_{\mathrm {1\,dB}}$ of more than 36%. The PAE at $\text{P}_{\mathrm {sat}}$ is 38% and 40% for the PA with nMOS and pMOS neutralizations, respectively. The AM–PM up to $\text{P}_{\mathrm {3\,dB}}$ for the PA with nMOS neutralization is 7°, and for the one with pMOS neutralization, it is less than 1.3° thanks to the proposed technique.

中文翻译：

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使用 pMOS 中和改进 33GHz CMOS SOI 功率放大器中的 AM-PM

这封信展示了两种适用于 5G 应用的高效两级功率放大器 (PA)，它们采用 22 纳米绝缘体上硅 (SOI) CMOS 技术实现。通过精心设计功率单元和优化布局来实现高效率。电容中和用于提高稳定性和增益。除了在第一个 PA 中使用 nMOS 中和电容器之外，两个 PA 都相似。在第二个 PA 中，我们建议使用 pMOS 电容器来同时显着提高稳定性和 AM-PM 线性度。对于两个 PA，饱和输出功率为 12.7 dBm 和 $\text{P}_{\mathrm {1\,dB}}$ 在 33 GHz 的 0.9-V 电源下为 11.9 dBm，功率附加效率 (PAE) 为 $\text{P}_{\mathrm {1\,dB}}$ 超过 36%。PAE 在 $\text{P}_{\mathrm {sat}}$ 对于具有 nMOS 和 pMOS 中和的 PA，分别为 38% 和 40%。AM-PM 至 $\text{P}_{\mathrm {3\,dB}}$ 对于具有 nMOS 中和的 PA，对于具有 pMOS 中和的 PA，由于所提出的技术，它小于 1.3°。