This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

中文翻译：

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基于 VLSI 设计的 Rank-Order Filtering 使用 DCRAM 架构。

本文讨论了用于实时语音和图像处理应用的具有可屏蔽存储器的秩序滤波 (ROF) 的 VLSI 设计。该设计基于通用位切片 ROF 算法，使用称为双单元随机存取存储器 (DCRAM) 的特殊定义存储器来实现 ROF 的主要操作：阈值分解和极化。使用面向内存的架构，所提出的 ROF 处理器可以受益于高灵活性、低成本和高速度。DCRAM 可以执行位切片读取、部分写入和流水线处理。位切片读取和部分写入由可屏蔽寄存器驱动。通过递归执行bit-slicing read和partial write，DCRAM可以在成本和速度方面有效地实现ROF。建议的设计已使用 TSMC 0 实现。18 μm 1P6M 技术。如物理实现结果所示，内核尺寸为 356.1 × 427.7μm(2) 并且 ROF 的 VLSI 实现可以在 256 MHz 下运行，1.8V 电源。