Hardware artificial neural network (ANN) systems with high density synapse array devices can perform massive parallel computing for pattern recognition with low power consumption. To implement a neuromorphic system with on-chip training capability, we need to develop an ideal synapse device with various device requirements, such as scalability, MLC characteristics, low power operation, data retention, and symmetric/linear conductance changes under potentiation/depression modes. Although various devices have been proposed for synapse applications, they have limitations for application in neuromorphic systems. In this paper, we will cover various RRAM synapse devices, such as filamentary switching RRAM (HfOx, TaOx, Cu-CBRAM) and analog RRAM devices, based on interface resistive switching (Pr0.7Ca0.3MnOx and TiOx) and ferroelectric polarization (HfZrOx). By optimizing potentiation/depression conditions, we could improve the conductance linearity and MLC characteristics of filamentary synapse devices. Interface RRAM has better MLC characteristics with limited retention and conductance linearity. By controlling the reactivity of metal electrodes and the oxygen concentration in oxides, we can modulate the synapse characteristics. Metal-Ferroelectric-Insulator-Semiconductor (MFIS) FET devices exhibit good retention characteristics and analog memory characteristics due to polarization. Based on various synapse device characteristics, we have estimated the pattern recognition accuracy of MNIST handwritten digits and CIFAR-10 datasets. We have confirmed that synapse device characteristics directly affect the pattern recognition accuracy of ANNs. In order to simultaneously satisfy all the requirements of synapse devices, it is necessary to develop new technology capable of controlling the movement of oxygen vacancies and metal ions at the atomic scale. Considering the limited synapse characteristics of current 2-terminal RRAM devices, hardware ANNs capable of only off-chip training can be constructed by optimizing the current RRAM devices by limiting the bit number. A 3-terminal synapse device or a device based on a new operation principle should be developed as an alternative for on-chip training applications.

中文翻译：

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基于RRAM的神经形态系统突触设备。

具有高密度突触阵列设备的硬件人工神经网络（ANN）系统可以执行低功耗的大规模并行计算以进行模式识别。为了实现具有片上训练能力的神经形态系统，我们需要开发一种具有各种设备要求的理想突触设备，例如可扩展性，MLC特性，低功耗操作，数据保留以及在增强/抑制模式下对称/线性电导率变化。尽管已经提出了用于突触应用的各种设备，但是它们在神经形态系统中的应用具有局限性。在本文中，我们将介绍基于接口电阻切换（Pr0.7Ca0）的各种RRAM突触设备，例如丝状开关RRAM（HfOx，TaOx，Cu-CBRAM）和模拟RRAM设备。3MnOx和TiOx）和铁电极化（HfZrOx）。通过优化增强/抑制条件，我们可以改善丝状突触设备的电导线性度和MLC特性。接口RRAM具有更好的MLC特性，且保留和电导率线性有限。通过控制金属电极的反应性和氧化物中的氧浓度，我们可以调节突触特性。金属铁电绝缘体半导体（MFIS）FET器件由于极化而具有良好的保持特性和模拟存储特性。基于各种突触设备特性，我们估计了MNIST手写数字和CIFAR-10数据集的模式识别准确性。我们已经证实，突触设备特性直接影响人工神经网络的模式识别精度。为了同时满足突触装置的所有要求，有必要开发能够控制氧空位和金属离子在原子尺度上运动的新技术。考虑到当前2端子RRAM设备的有限突触特性，可以通过限制位数来优化当前RRAM设备，从而构建仅能够进行片外训练的硬件ANN。应开发3端突触设备或基于新操作原理的设备作为片上培训应用程序的替代产品。考虑到当前2端子RRAM设备的有限突触特性，可以通过限制位数来优化当前RRAM设备，从而构建仅能够进行片外训练的硬件ANN。应开发3端突触设备或基于新操作原理的设备作为片上培训应用程序的替代产品。考虑到当前2端子RRAM设备的有限突触特性，可以通过限制位数来优化当前RRAM设备，从而构建仅能够进行片外训练的硬件ANN。应开发3端突触设备或基于新操作原理的设备作为片上培训应用程序的替代产品。