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Power Frequency Harmonic Reduction and its Re-Distribution for Improved Filter Design in Current-fed Switched Inverter
IEEE Transactions on Industrial Electronics ( IF 7.7 ) Pub Date : 2019-06-01 , DOI: 10.1109/tie.2018.2860531
Anil Gambhir , Santanu K. Mishra , Avinash Joshi

Due to the pulsating power at the inverter output terminals, the passive storage elements of the boost stage of the current-fed switched inverter (CFSI) contain a power frequency harmonic component (100 Hz), apart from dc and switching frequency components. In prior designs, the second harmonic component is suppressed by increasing the size of the input filter inductor and capacitor or by using additional circuits. This paper presents a complete characterization of a control-based approach to suppress the power frequency harmonic component in the input inductor current of a CFSI. It also presents a comprehensive characterization of the harmonic power redistribution. Using the proposed approach, it is demonstrated that the inductor value of a CFSI is reduced by 61% for the same peak-to-peak ripple. This leads to an improvement in the conversion ratio, efficiency, and power density of the overall converter. A SiC MOSFET-based CFSI with 75-kHz switching frequency is used to verify the proposed design philosophy.

中文翻译:

用于改进电流馈电开关逆变器滤波器设计的工频谐波降低及其再分配

由于逆变器输出端的脉动功率,电流馈电开关逆变器 (CFSI) 升压级的无源存储元件除了直流和开关频率分量外,还包含工频谐波分量 (100 Hz)。在现有设计中,通过增加输入滤波电感器和电容器的尺寸或通过使用附加电路来抑制二次谐波分量。本文介绍了一种基于控制的方法的完整表征,以抑制 CFSI 输入电感器电流中的工频谐波分量。它还提供了谐波功率再分配的综合特征。使用所提出的方法,证明对于相同的峰峰值纹波,CFSI 的电感值降低了 61%。这导致整个转换器的转换比、效率和功率密度的改进。具有 75 kHz 开关频率的基于 SiC MOSFET 的 CFSI 用于验证提议的设计理念。
更新日期:2019-06-01
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