This paper presents the characterization of network delays in an IEC61850 process bus substation area network, both through theoretical analysis and simulations. Several design targets were defined considering the recommendations of standards and good design practices: number of network hops, total network delay, probability of the delay being exceeded, link load, network topology and availability. An analytical delay estimation methodology is proposed, considering both the steady-state traffic and traffic resulting from a breaker failure event. A complete substation is taken as an example for characterizing the network delays, considering a star network topology. Simulations allow to obtain the cumulative distribution functions and percentile values of network delays. Results show a good agreement between the simulation and the analytical analysis. While the delay is best characterized statistically through simulation, finding the maximum network delay through simulations can be very time consuming, making the analytical analysis more suitable.

中文翻译：

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变电站过程总线网络延迟的表征


本文通过理论分析和仿真描述了 IEC61850 过程总线变电站区域网络中网络延迟的特征。考虑到标准的建议和良好的设计实践，定义了几个设计目标：网络跳数、总网络延迟、超过延迟的概率、链路负载、网络拓扑和可用性。提出了一种分析延迟估计方法，考虑了稳态流量和断路器故障事件产生的流量。以一个完整的变电站为例，考虑星形网络拓扑来表征网络延迟。模拟可以获得网络延迟的累积分布函数和百分位值。结果表明模拟和分析之间具有良好的一致性。虽然通过仿真可以最好地从统计角度表征延迟，但通过仿真找到最大网络延迟可能非常耗时，因此分析分析更合适。