Modern field-programmable gate arrays (FPGAs) operate at a core voltage around 1 V and therefore even small voltage fluctuations lead to timing violations and logic errors. The power delivery network (PDN) between the voltage regulator and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. Simulation tools are commonly used to estimate the impedance, however, they do not account for aging, component variations, and inaccurate modeling of parasitic elements, all of which lead to PDN design deviation. In this paper, two schemes are presented: first, to extract the dc resistance in the power delivery path, and second, to identify the high impedance frequency band(s) in the PDN. The embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc–dc converter. A new self-calibrated carry-chain-based analog-to-digital converter (CC-ADC) is used for high-speed sampling of the core voltage. The proposed schemes are demonstrated on an Intel Cyclone IV FPGA board. Real-time IR-drop compensation is shown to eliminate logic errors in an finite impulse response filter application. It is also shown that the fail/pass map of a crossbar application matches well with the extracted impedance profile versus voltage and frequency. By modifying the PDN based on the extracted results, the voltage operating range and reliability of the crossbar application are greatly extended.

中文翻译：

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FPGA 中的频域供电网络自表征以提高系统可靠性

现代现场可编程门阵列 (FPGA) 在大约 1 V 的核心电压下运行，因此即使很小的电压波动也会导致时序违规和逻辑错误。稳压器和 FPGA 内核之间的供电网络 (PDN) 必须经过精心设计，以在广泛的频率范围内实现低输出阻抗。仿真工具通常用于估计阻抗，但是，它们不考虑老化、组件变化和寄生元件的不准确建模，所有这些都会导致 PDN 设计偏差。在本文中，提出了两种方案：首先，提取供电路径中的直流电阻，其次，识别 PDN 中的高阻抗频带。嵌入式阻抗提取工具在 FPGA 负载内合成，与混合信号电流模式 dc-dc 转换器配合使用。新的基于进位链的自校准模数转换器 (CC-ADC) 用于对内核电压进行高速采样。建议的方案在英特尔 Cyclone IV FPGA 板上进行了演示。显示实时 IR 压降补偿可消除有限脉冲响应滤波器应用中的逻辑错误。还显示交叉开关应用的失败/通过图与提取的阻抗曲线与电压和频率的关系很好地匹配。通过根据提取的结果修改 PDN，交叉开关应用的电压工作范围和可靠性得到了极大的扩展。建议的方案在英特尔 Cyclone IV FPGA 板上进行了演示。显示实时 IR 压降补偿可消除有限脉冲响应滤波器应用中的逻辑错误。还显示交叉开关应用的失败/通过图与提取的阻抗曲线与电压和频率的关系很好地匹配。通过根据提取的结果修改 PDN，交叉开关应用的电压工作范围和可靠性得到了极大的扩展。建议的方案在英特尔 Cyclone IV FPGA 板上进行了演示。显示实时 IR 压降补偿可消除有限脉冲响应滤波器应用中的逻辑错误。还显示交叉开关应用的失败/通过图与提取的阻抗曲线与电压和频率的关系很好地匹配。通过根据提取的结果修改 PDN，交叉开关应用的电压工作范围和可靠性得到了极大的扩展。