Space solar array simulators (SSASs), which are used for testing space power systems, generally utilize linear power topologies owing to their fast dynamic performance and satisfactory simulation accuracy. However, to output a medium power level from a linear-power-topology SSAS, multiple parallel linear voltage-controlled current sources are required for addressing the redundant power dissipation, thereby limiting the overall mechanical structure and volume optimization; in addition, the presence of multiple parallel sources results in a complex circuit structure with poor reliability. In this context, in this study, we propose a novel three-port linear power composite transistor as a linear power dissipation device, which is composed of multiple cascaded SiC-JFETs to improve on the above-mentioned shortcomings. The proposed 510-W optimized SSAS requires only eight parallel linear current-source paths to form a linear power stage and uses a high-speed field-programmable gate array (FPGA) digital controller to quickly react to a load step between short circuit and open circuit (the harshest working condition for a solar array simulator) at a 1-kHz stepping frequency. Further, the device can react to a load step between short circuit and the nominal working point at 10-kHz stepping frequency, thus, offering a better dynamic performance over other similar devices.

中文翻译：

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基于多个级联SiC-JFET的新型三端口线性功率复合晶体管空间太阳能阵列模拟器的优化设计


用于测试空间电源系统的空间太阳能电池阵列模拟器（SSAS）通常采用线性电源拓扑，因为其具有快速的动态性能和令人满意的模拟精度。然而，为了从线性功率拓扑SSAS输出中等功率水平，需要多个并行的线性压控电流源来解决冗余功耗，从而限制了整体机械结构和体积优化；另外，多个并行源的存在导致电路结构复杂，可靠性差。在此背景下，在本研究中，我们提出了一种新型三端口线性功率复合晶体管作为线性功耗器件，它由多个级联的SiC-JFET组成，以改善上述缺点。所提出的 510W 优化 SSAS 仅需要八个并行线性电流源路径即可形成线性功率级，并使用高速现场可编程门阵列 (FPGA) 数字控制器对短路和开路之间的负载阶跃快速做出反应电路（太阳能电池阵列模拟器最恶劣的工作条件）在 1kHz 步进频率。此外，该器件可以以 10kHz 步进频率对短路和标称工作点之间的负载阶跃做出反应，从而提供比其他类似器件更好的动态性能。