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Resistive Neural Hardware Accelerators
Proceedings of the IEEE ( IF 23.2 ) Pub Date : 2023-05-16 , DOI: 10.1109/jproc.2023.3268092
Kamilya Smagulova 1 , Mohammed E. Fouda 2 , Fadi Kurdahi 2 , Khaled N. Salama 1 , Ahmed Eltawil 1
Affiliation  

Deep neural networks (DNNs), as a subset of machine learning (ML) techniques, entail that real-world data can be learned, and decisions can be made in real time. However, their wide adoption is hindered by a number of software and hardware limitations. The existing general-purpose hardware platforms used to accelerate DNNs are facing new challenges associated with the growing amount of data and are exponentially increasing the complexity of computations. Emerging nonvolatile memory (NVM) devices and the compute-in-memory (CIM) paradigm are creating a new hardware architecture generation with increased computing and storage capabilities. In particular, the shift toward resistive random access memory (ReRAM)-based in-memory computing has great potential in the implementation of area- and power-efficient inference and in training large-scale neural network architectures. These can accelerate the process of IoT-enabled AI technologies entering our daily lives. In this survey, we review the state-of-the-art ReRAM-based DNN many-core accelerators, and their superiority compared to CMOS counterparts was shown. The review covers different aspects of hardware and software realization of DNN accelerators, their present limitations, and prospects. In particular, a comparison of the accelerators shows the need for the introduction of new performance metrics and benchmarking standards. In addition, the major concerns regarding the efficient design of accelerators include a lack of accuracy in simulation tools for software and hardware codesign.

中文翻译:


电阻式神经硬件加速器



深度神经网络 (DNN) 作为机器学习 (ML) 技术的子集,需要能够学习现实世界的数据并实时做出决策。然而,它们的广泛采用受到许多软件和硬件限制的阻碍。用于加速 DNN 的现有通用硬件平台正面临着与数据量不断增长相关的新挑战,并且计算的复杂性呈指数级增加。新兴的非易失性存储器 (NVM) 设备和内存计算 (CIM) 范式正在创建新一代硬件架构,具有增强的计算和存储能力。特别是,向基于电阻式随机存取存储器(ReRAM)的内存计算的转变在实现面积和功率高效推理以及训练大规模神经网络架构方面具有巨大潜力。这些可以加速物联网人工智能技术进入我们日常生活的进程。在本次调查中,我们回顾了最先进的基于 ReRAM 的 DNN 众核加速器,并显示了它们与 CMOS 同类产品相比的优越性。该综述涵盖了 DNN 加速器硬件和软件实现的不同方面、它们目前的局限性和前景。特别是,加速器的比较表明需要引入新的性能指标和基准测试标准。此外,有关加速器高效设计的主要问题包括软件和硬件协同设计的仿真工具缺乏准确性。
更新日期:2023-05-16
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