The interface trap density (Dit) of the SiO2/β-Ga2O3 interface in ( 2¯01), (010), and (001) orientations is obtained by the Hi-Lo method with the low frequency capacitance measured using the Quasi-Static Capacitance-Voltage (QSCV) technique. QSCV measurements are carried out at higher temperatures to increase the measured energy range of Dit in the bandgap. At room temperature, higher Dit is observed near the band edge for all three orientations. The measurement at higher temperatures led to an annealing effect that reduced the Dit value for all samples. Comparison with the conductance method and frequency dispersion of the capacitance suggests that the traps at the band edge are slow traps which respond to low frequency signals.

中文翻译：

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SiO2/β-Ga2O3 界面在不同晶体取向上的温度相关准静态电容-电压表征

SiO2/β-Ga2O3 界面在 (2¯01)、(010) 和 (001) 方向的界面陷阱密度 (Dit) 通过 Hi-Lo 方法获得，低频电容使用准静态测量电容电压 (QSCV) 技术。QSCV 测量在较高温度下进行，以增加带隙中 Dit 的测量能量范围。在室温下，在所有三个方向的带边缘附近都观察到更高的 Dit。在较高温度下进行测量会导致退火效应，从而降低所有样品的 Dit 值。与电容的电导方法和频率色散的比较表明，带边缘的陷阱是响应低频信号的慢陷阱。