曹鹏 - 东南大学 - 集成电路学院

个人简介

东南大学集成电路学院，副教授，博士生导师，任职于东南大学集成电路学院国家ASIC工程中心（简称“国家ASIC中心”）和国家集成电路设计自动化技术创新中心（简称“EDA国创中心”），长期专注于宽电压电路时序分析和签核方法，研究基于AI的下一代EDA设计方法学，近年来在IEEE TVLSI，IEEE TCAD, DAC, ICCAD, ASP-DAC, ISCAS等电路设计和EDA领域顶级期刊和会议发表论文30余篇，并获2019年和2022年 ASP-DAC会议最佳论文提名，担任IEEE TCAS-I, TCAS-II, TCAD, TVLSI等期刊审稿人，授权发明专利30余件，授权美国专利5件，作为负责人承担多项国家重点研发计划课题、国家自然科学基金课题及江苏省自然科学基金课题，依托东南大学与华大九天、国微、华为海思等国内顶尖EDA企业及设计公司成立的联合实验室，作为负责人承担多个EDA合作研发项目，技术成果应用于国产EDA企业，获国家科技进步二等奖、中国专利金奖、江苏省科技进步一等奖，指导学生获得2024年国际ICCAD竞赛全球第3名，2023年集成电路EDA设计精英挑战赛最高奖菁英杯，并获得多项一等奖。教育经历 1998.9-2002.6，东南大学无线电工程系，获工学学士学位； 2002.7-2010.3 东南大学电子科学与工程学院，硕博连读，获工学博士学位。工作经历 2010.3-2015.7 东南大学电子科学与工程学院，讲师； 2015.7-2023.1 东南大学电子科学与工程学院，副教授； 2023.1-至今转至集成电路学院。

研究领域

宽电压电路时序分析和签核方法、基于AI的EDA设计方法

近期论文

查看导师新发文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

1. [C22] Y. Dong, J. Jiao, H. Zhang, Y. Qin, Z. Deng, X. Cheng, and P. Cao , Fast and Effective Logic Gate Sizing Based on Heterogeneous Graph Neural Network, in Proc. Int. Symp. Electron. Design Autom. (ISEDA) , May 2025, pp. 1-6. 2. [C21] H. Zhang, X. Cheng, J. Jiao, Y. Qin, and P. Cao , OSCC-SA: Detecting Oscillation in Strongly Connected Components Using Static Analysis, in Proc. Int. Symp. Electron. Design Autom. (ISEDA) , May 2025, pp. 1-6. 3. [C20] T. Bai, Z. Deng, and P. Cao , Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning, in Proc. ACM/IEEE Int. Symp. Mach. Learn. CAD (MLCAD) , Sep. 2024, pp. 1–7. 4. [C19] Z. Zhang, W. Ding, G. He, and P. Cao , LAG-Sizer: A Novel Gate Sizer Based on Leak Generative Adversarial Network with Feature Fusion, in *Proc. 43rd IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD)*, Apr. 2024, pp. 1–9. 5. [C18] W. Ding, Z. Zhang, G. He, and P. Cao , A Physical and Timing Aware Placement Optimization Framework Based on Graph Neural Network, in *Proc. 43rd IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD)*, Apr. 2024, pp. 1–9. 6. [C17] Z. Cui, T. Zhang, Y. Cai, P. Cao , T.-J. Lin, and L. He, An Efficient Statistical Clock Skew Analysis Method for Clock Trees, in Proc. 2nd Int. Symp. Electron. Design Autom. (ISEDA) , May 2024, pp. 416–420. 7. [C16] X. Cheng, Y. Ye, G. He, Q. Song, and P. Cao , Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction, in *Proc. 29th Asia South Pac. Design Autom. Conf. (ASP-DAC)*, 2024, pp. 171–176. 8. [C15] G. He, W. Ding, Y. Ye, X. Cheng, Q. Song, and P. Cao , An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning, in *Proc. 29th Asia South Pac. Design Autom. Conf. (ASP-DAC)*, 2024, pp. 177–182. 9. [J05] P. Cao , G. He, W. Ding, Z. Zhang, K. Wang, and J. Yang, Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 31, no. 9, pp. 1413–1424, 2023. 10. [J04] P. Cao , G. He, and T. Yang, TF-Predictor: Transformer-Based Prerouting Path Delay Prediction Framework, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. , vol. 42, no. 7, pp. 2227–2237, 2023. 11. [J03] S. Shen, P. Cao , M. Ling, and L. Shi, A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. , vol. 42, no. 4, pp. 1223–1234, 2023. 12. [J02] P. Cao , T. Yang, K. Wang, W. Bao, and H. Yan, Topology-Aided Multicorner Timing Predictor for Wide Voltage Design, IEEE Des. Test , vol. 40, no. 1, pp. 62–69, 2023. 13. [C14] P. Cao and J. Wang, Late Breaking Results: RL-LPO: Reinforcement Learning Based Leakage Power Optimization Framework with Graph Neural Network, in *Proc. 60th ACM/IEEE Design Autom. Conf. (DAC)*, 2023, pp. 1–2. 14. [C13] Q. Song, X. Cheng, and P. Cao , Critical Paths Prediction under Multiple Corners Based on BiLSTM Network, in *Proc. 60th ACM/IEEE Design Autom. Conf. (DAC)*, 2023, pp. 1–6. 15. [C12] H. Jiang, X. Cheng, and P. Cao , Multiple-Input Switching Modeling with Graph Neural Network, in Proc. Int. Symp. Electron. Design Autom. (ISEDA) , 2023, pp. 428–432. 16. [C11] T. Yang, G. He, and P. Cao , Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework, in *Proc. 27th Asia South Pac. Design Autom. Conf. (ASP-DAC)*, 2022, pp. 184–189. 17. [C10] K. Wang and P. Cao , A Graph Neural Network Method for Fast ECO Leakage Power Optimization, in *Proc. 27th Asia South Pac. Design Autom. Conf. (ASP-DAC)*, 2022, pp. 196–201. 18. [J01] J. Guo, P. Cao , M. Li, Y. Gong, Z. Liu, G. Bai, and J. Yang, Semi-analytical Path Delay Variation Model with Adjacent Gates Decorrelation for Subthreshold Circuits, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. , pp. 931–944, 2021. 19. [C09] P. Cao , W. Bao, K. Wang, and T. Yang, A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy, in *Proc. 26th Asia South Pac. Design Autom. Conf. (ASP-DAC)*, 2021, pp. 291–296. 20. [C08] H. Yan, X. Shi, C. Xuan, P. Cao , and L. Shi, An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range, in *Proc. 26th Asia South Pac. Design Autom. Conf. (ASP-DAC)*, 2021, pp. 272–277. 21. [C07] H. Jiang, B. Xu, P. Cao , and H. Cai, Analytical Delay Model in Near-Threshold Domain Considering Transition Time, in Proc. IEEE Int. Conf. Integr. Circuits, Technol. Appl. (ICTA) , 2021, pp. 234–235. 22. [C06] J. Guo, P. Cao , M. Li, Z. Liu, and J. Yang, Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS) , 2020, pp. 1–5. 23. [C05] W. Bao, P. Cao , H. Cai, and A. Bu, A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design, in Proc. Great Lakes Symp. VLSI (GLSVLSI) , 2020, pp. 309–314. 24. [C04] P. Cao , Z. Liu, J. Wu, J. Guo, J. Yang, and L. Shi, A Statistical Timing Model for Low Voltage Design Considering Process Variation, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD) , 2019, pp. 1–8. 25. [C03] P. Cao , Z. Liu, B. Xu, and J. Guo, A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time, in Proc. IEEE Int. Conf. Electron., Circuits, Syst. (ICECS) , 2019, pp. 586–589. 26. [C02] P. Cao , J. Wu, Z. Liu, J. Guo, J. Yang, and L. Shi, A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region, in Proc. Great Lakes Symp. VLSI (GLSVLSI) , 2019, pp. 323–326. 27. [C01] P. Cao , Z. Liu, J. Guo, H. Pang, J. Wu, and J. Yang, Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region, in Proc. IEEE Int. New Circuits Syst. Conf. (NEWCAS) , 2019, pp. 1–4.

学术兼职

担任IEEE TCAS-I, TCAS-II, TCAD, TVLSI等期刊审稿人