刘雷波 - 清华大学 - 集成电路学院

个人简介

清华大学集成电路学院长聘教授、博士生导师，教育部长江学者特聘教授，国家级一流本科课程负责人。 1999年和2004年分别在清华电子工程系和微电子所获得学士和博士学位。2004年留在清华微电子所任教，2006年~2017年分别在欧洲微电子中心、麻省理工学院、林肯大学、牛津大学进修与访问。长期从事软件定义芯片、硬件安全和密码芯片、VLSI数字信号处理等的研究工作。发表高水平论文300余篇、授权发明专利150余项（美国专利20余项）、撰写著作9部/译作4部、参与制定国家标准1项。担任国际权威期刊《IEEECircuits and Systems》副主编、中国工程院院刊《信息与电子工程前沿》执行副主编；电子设计自动化领域顶级会议DAC的TPC委员，密码硬件领域顶级会议CHES的TPC委员，固态电路一流会议IEEE A-SSCC的大会主席等；中国密码学会密码芯片专委会副主任委员；ISO/IECJTC1/SC27 国际标准注册专家。关键技术在一系列国家重大工程中取得批量应用。获国家技术发明二等奖、中国专利金奖、教育部技术发明一等奖、中国电子学会技术发明一等奖、世界互联网大会15项世界互联网领先科技成果等科技奖励。主持3门课, 获首批国家级一流本科课程、清华大学本科生精品课、北京市青年教师教学竞赛一等奖、清华大学青年教师教学竞赛一等奖、清华大学青年教师教学优胜奖、MOOC教学先锋奖等多个教学奖励。所负责的大规模网络开放课程（MOOC）入选首批教育部高校在线教学国际平台。

研究领域

长期从事软件定义芯片、硬件安全和密码芯片、VLSI数字信号处理等的研究工作

近期论文

查看导师最新文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

L.Liu, A. Luo, G. Li, J. Zhu, Y. Wang, G. Shan, J. Pan, S. Yin, S. Wei.“Jintide?: A Hardware Security Enhanced Server CPU with Xeon?Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Computing Processor”.31st Hot Chips: A Symposium on High Performance Chips( Hot Chips 2019), Stanford, Palo Alto, CA, USA, 18-20, August, 2019 L. Liu, J. Zhu, Z. Li, Y. Lu, Y. Deng, J. Han, S. Yin, S. Wei, “A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges and Applications”,ACM Computing Survey, 2019 Z. Li,*L. Liu, Y. Deng, S. Yin, Y. Wang, S. Wei, “Aggressive Parallelization of Irregular Applications on Reconfigurable Hardware,”in the 44thInternational Symposium on Computer Architecture (ISCA), Toronto, Canada, June,2017, pp. 575-586. DOI:10.1145/3140659.3080228 G. Peng,L. Liu*, S. Zhou, S. Yin, S. Wei. "A 2.92 Gbps/W and 0.43 Gbps/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection."IEEE Journal of Solid State Circuits, 2019. DOI：10.1109/JSSC. 2019.2952839 Z. Li, *L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei. "FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory".In The 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52), October 12-16, 2019, Columbus, OH, USA. Q. Wang,*L. Liu, W. Zhu, H. Mo, C. Deng, S. Wei, “A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment,”in the 54th Annual Design Automation Conference (DAC 2017),Austin, TX, USA, June 2017, pp.57-57.DOI:10.1145/3061639.3062182[Best Paper Nomination]. Y. Yang, Z. Li, Y. Deng, Z. Liu,S. Yin, S. Wei,L. Liu*, "GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent",In 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA),2020. D. Chen,Z. Li, T. Xiong, Z. Liu, J. Yang, S. Yin, S. Wei,L. Liu*, “CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture”,In The 53nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-53), October 17-21, 2020. H. Mo, L. Liu*, W. Hu, W. Zhu, Q. Li, A. Li, S. Yin, J. Chen, X. Jiang, S, Wei,“TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks”,In The 53nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-53), October 17-21, 2020. N. Zhang, B. Yang, C. Chen, S. Yin, S. Wei,L. Liu*,"Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT",Conferenceon Cryptographic Hardware and Embedded Systems,(CHES2020),Beijing, China, 14-17, September, 2020.