尹首一 - 清华大学 - 集成电路学院

个人简介

博士，清华大学教授，集成电路学院副院长，国家杰出青年科学基金获得者，国家“新一代人工智能”重大项目专家组成员。研究方向为人工智能芯片设计、可重构计算、新型处理器体系结构。已发表学术论文200余篇，包括IEEE JSSC、TPDS、TCSVT、TVLSI、TCAS-I/II和ISSCC、ISCA、VLSI、DAC、HPCA等集成电路和体系结构领域权威期刊和学术会议。出版《可重构计算》、《人工智能芯片设计》专著2部。曾获国家技术发明二等奖、中国电子学会技术发明一等奖、中国发明专利金奖、教育部技术发明一等奖、江西省科技进步二等奖、中国电子学会优秀科技工作者奖、中国电子信息领域优秀科技论文奖。现任集成电路领域国际会议IEEE DAC、ICCAD、DATE、ASPDAC和A-SSCC的技术委员会委员，国际期刊《IEEE Transactions on Circuits and System I: Regular Papers》、《ACM Transactions on Reconfigurable Technology and Systems》及《Integration, the VLSI Journal》的Associate Editor。

研究领域

人工智能芯片设计、可重构计算、新型处理器体系结构

近期论文

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Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Leibo Liu, Shaojun Wei: A 1.06-to-5.09 TOPS/W Reconfigurable Hybrid-Neural-Network Processor for Deep Learning Applications. VLSI 2017 Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei: A Reconfigurable Multi-modal Neural Processor for Cognitive Intelligence Applications. ISSCC-SRP 2017 Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei: Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. IEEE TVLSI 2017 Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei:Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. ISCA 2017 Shuang Liang, Shouyi Yin, Leibo Liu, Yike Guo, Shaojun Wei:A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. IEEE CAL 2016 Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei: Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual-Vdd CGRAs. IEEE TCAD 2016 Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. IEEE TCAS II 2016 Shouyi Yin, Xinhan Lin, Leibo Liu, Shaojun Wei: Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures. IEEE TPDS 2016 Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, Shaojun Wei: Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. IEEE TVLSI 2016 Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu, Shaojun Wei: A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. IEEE TVLSI 2016 Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei: Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. IEEE TVLSI 2016 Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei: Trigger-Centric Loop Mapping on CGRAs. IEEE TVLSI 2016 Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei: Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. ICCAD 2016 Peng Ouyang, Shouyi Yin, Yuchi Zhang, Leibo Liu, Shaojun Wei: A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency. IEEE TCAS II 2015 Dajiang Liu, Shouyi Yin, Yu Peng, Leibo Liu, Shaojun Wei: Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures. IEEE TVLSI 2015 Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei: Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms. IEEE TVLSI 2015 Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space. CICC 2015 Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: RNA: a reconfigurable architecture for hardware neural acceleration. DATE 2015 Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei: Acceleration of Nested Conditionals on CGRAs via Trigger Scheme. ICCAD 2015 Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: Neural approximating architecture targeting multiple application domains. ISCAS 2015 Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei: Polyhedral model based mapping optimization of loop nests for CGRAs. DAC 2013