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High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2
Small ( IF 12.1 ) Pub Date : 2023-02-07 , DOI: 10.1002/smll.202207927
Xionghui Jia Zhixuan Cheng Bo Han Xing Cheng Qi Wang Yuqia Ran Wanjin Xu Yanping Li Peng Gao Lun Dai

In this work, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS2 and p-MoTe2 grown by the chemical vapor deposition method. In the CMOS device, the n- and p-channel field-effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO2 is used as the gate dielectric. An Al2O3 seed layer is used to protect the MoS2 from heavily n-doping in the later-on atomic layer deposition process. P-MoTe2 FET is intentionally designed as the upper layer. Because p-doping of MoTe2 results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe2. An HfO2 capping layer is employed to further balance the transfer curves of n- and p-channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at VDD of 1 V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at VDD of 1 V. This work demonstrates the advantage of two-dimensional semi-conductive transition metal dichalcogenides in fabricating high-density integrated circuits.

中文翻译:

具有基于 CVD 生长的 n-MoS2 和 p-MoTe2 的单片 3D 架构的高性能 CMOS 反相器阵列

在这项工作中,基于通过化学气相沉积法生长的大规模n-MoS 2和p-MoTe 2 ,制造了单片三维互补金属氧化物半导体(CMOS)反相器阵列。在 CMOS 器件中,n 和 p 沟道场效应晶体管 (FET) 垂直堆叠并共享同一栅电极。高k HfO 2用作栅极电介质。Al 2 O 3种子层用于保护MoS 2免受后续原子层沉积工艺中的重n掺杂。P-MoTe 2 FET 被有意设计为上层。由于 MoTe 2的 p 型掺杂由于空气中的氧气和水分,这种设计可以保证更高的MoTe 2孔密度。采用HfO 2覆盖层进一步平衡 n 和 p 沟道 FET 的传输曲线并提高反相器的性能。CMOS 器件的典型增益和功耗分别约为 4.2 和 0.11 nW,V DD为 1 V。统计结果表明,CMOS 阵列具有很高的器件良率(60%),平均电压增益值为在 1 V 的V DD时约为 3.6 。这项工作证明了二维半导体过渡金属二硫化物在制造高密度集成电路中的优势。
更新日期:2023-02-07
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