As the complexity and scope of VLSI designs continue to grow, fault detection processes in the pre-silicon stage have become crucial to guaranteeing reliability in IC design. Most fault detection algorithms can be solved by transforming them into a satisfiability (SAT) problem decipherable by SAT solvers. However, SAT solvers consume significant computational time, as a result of the search space explosion problem. This ever- increasing amount of data can be handled via machine learning techniques known as deep learning algorithms. In this paper, we propose a new approach utilizing deep learning for fault detection (FD) of combinational and sequential circuits in a type of stuck-at-faults. The goal of the proposed semi-supervised FD model is to avoid the search space explosion problem by taking advantage of unsupervised and supervised learning processes. First, the unsupervised learning process attempts to extract underlying concepts of data using Deep sparse autoencoder. Then, the supervised process tends to describe rules of classification that are applied to the reduced features for detecting different stuck-at faults within circuits. The FD model proposes good performance in terms of running time about 187 × compared to other FD algorithm based on SAT solvers. In addition, it is compared to common classical machine learning models such as Decision Tree (DT), Random Forest (RF) and Gradient Boosting (GB) classifiers, in terms of validation accuracy. The results show a maximum validation accuracy of the feature extraction process at 99.93%, using Deep sparse autoencoder for combinational circuits. For sequential circuits, stacked sparse autoencoder presents 99.95% as average validation accuracy. The fault detection process delivers around 99.6% maximum validation accuracy for combinational circuits from ISCAS’85 and 99.8% for sequential circuits from ISCAS’89 benchmarks. Moreover, the proposed FD model has achieved a running time of about 1.7x, compared to DT classifier and around 1.6x, compared to RF classifier and GB machine learning classifiers, in terms of validation accuracy in detecting faults occurred in eight different digital circuits. Furthermore, the proposed model outperforms other FD models, based on Radial Basis Function Network (RBFN), achieving 97.8% maximum validation accuracy.

随着 VLSI 设计的复杂性和范围不断扩大，硅前阶段的故障检测过程对于保证 IC 设计的可靠性变得至关重要。大多数故障检测算法可以通过将它们转换为可被 SAT 求解器破译的可满足性 (SAT) 问题来解决。但是，由于搜索空间爆炸问题，SAT 求解器会消耗大量计算时间。这种不断增加的数据量可以通过称为深度学习算法的机器学习技术来处理。在本文中，我们提出了一种利用深度学习对组合电路和时序电路进行故障检测（FD）的新方法。所提出的半监督 FD 模型的目标是通过利用无监督和监督学习过程来避免搜索空间爆炸问题。首先，无监督学习过程尝试使用深度稀疏自动编码器提取数据的基本概念。然后，监督过程倾向于描述应用于简化特征的分类规则，以检测电路内不同的固定故障。与其他基于 SAT 求解器的 FD 算法相比，FD 模型在运行时间方面提出了良好的性能，约为 187 倍。此外，在验证准确性方面，它与常见的经典机器学习模型，如决策树 (DT)、随机森林 (RF) 和梯度提升 (GB) 分类器进行了比较。结果显示，使用深度稀疏自动编码器进行组合电路的特征提取过程的最大验证准确率为 99.93%。对于时序电路，堆叠稀疏自动编码器的平均验证准确率为 99.95%。故障检测过程为 ISCAS'85 的组合电路提供大约 99.6% 的最大验证准确度，为 ISCAS'89 基准的时序电路提供 99.8% 的最大验证准确度。此外，与 DT 分类器相比，所提出的 FD 模型的运行时间约为 1.7 倍，与 RF 分类器和 GB 机器学习分类器相比，在检测八种不同数字电路中发生的故障的验证准确性方面，该模型的运行时间约为 1.6 倍。此外，所提出的模型优于其他基于径向基函数网络 (RBFN) 的 FD 模型，达到 97。