This letter presents a 26–34.5-GHz power amplifier (PA) fabricated in 65-nm bulk CMOS with a core area of 0.338 mm². To reduce the mismatch in the conversion between single-ended and differential signals, the symmetry of the baluns is analyzed in detail. To achieve a broadband operation, a wideband source impedance matching network is introduced. The measured small signal gain is 25.1 dB, and the proposed PA achieves 21.6-dBm saturated output power ( $P_{\mathrm {sat}}$ ) with 30.4% peak power-added efficiency (PAE) as well as OP_{1 dB} of 20.4 dBm with 29.4% PAE at 29 GHz. The 1-dB bandwidth of $P_{\mathrm {sat}}$ is from 26 to 34.5 GHz.

中文翻译：

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具有平衡失配减少和级间匹配的 26–34.5GHz 功率放大器的设计和分析

这封信介绍了一个 26-34.5-GHz 功率放大器 (PA)，它采用 65-nm 体 CMOS 制造，核心面积为 0.338 mm ²。为了减少单端和差分信号之间转换的失配，对巴伦的对称性进行了详细分析。为了实现宽带操作，引入了宽带源阻抗匹配网络。测得的小信号增益为 25.1 dB，建议的 PA 实现了 21.6-dBm 的饱和输出功率（ $P_{\mathrm {sat}}$)，峰值功率附加效率 (PAE) 为 30.4%，OP _{1 dB}为 20.4 dBm，29 GHz 时 PAE 为 29.4%。的 1-dB 带宽 $P_{\mathrm {sat}}$从 26 到 34.5 GHz。