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An Ultra-Low Quiescent Current Under-Voltage Lockout Circuit for a High-Voltage Gate Driver IC
Electronics ( IF 2.9 ) Pub Date : 2020-10-20 , DOI: 10.3390/electronics9101729
Kunhee Cho

An ultra-low quiescent current under-voltage lockout (UVLO) circuit for a high-voltage gate driver integrated circuit (HVIC) is described for application in portable devices. The UVLO circuit consumes the static current in the high-side circuitry and the resistive divider used to detect the supply-voltage was the major consumer of power in the circuit. Hence, a supply-voltage sensor based on a diode-connected metal–oxide–semiconductor field-effect transistor (MOSFET) with a voltage limiter design is proposed to ensure low power consumption. Unlike the conventional UVLO design, where a resistive divider is used, the proposed structure dissipates the negligible current at a low supply-voltage and significantly reduces the static current at the nominal and high supply-voltage. The high-side quiescent current using the proposed design and the conventional designs at various supply-voltage levels are analyzed. In the proposed structure, the size of the voltage sensor is considerably smaller when compared with those in conventional designs.

中文翻译:

高压栅极驱动器IC的超低静态电流欠压锁定电路

描述了用于高压栅极驱动器集成电路(HVIC)的超低静态电流欠压锁定(UVLO)电路,用于便携式设备。UVLO电路消耗高端电路中的静态电流,而用于检测电源电压的电阻分压器则是电路中功率的主要消耗者。因此,为确保低功耗,提出了一种基于二极管连接的金属氧化物半导体场效应晶体管(MOSFET)的电源电压传感器,并带有限压器设计。与使用电阻分压器的常规UVLO设计不同,该结构在低电源电压下耗散了可忽略的电流,并在额定电压和高电源电压下显着降低了静态电流。分析了使用所建议的设计和常规设计在各种电源电压水平下的高端静态电流。在所提出的结构中,与常规设计相比,电压传感器的尺寸明显较小。
更新日期:2020-10-20
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