Abstract

This work presents an Operation Transconductance Amplifier with improved common mode rejection based in both Nauta’s and Vieru’s push–pull based OTAs operating at a 0.5 V power supply in the 180 nm CMOS process, with an additional biasing circuit that employs an adaptive body bias technique for calibration of output common mode voltage. Equal size CMOS push–pull pair inverter cells comprised by rectangular and trapezoidal transistor arrays are simulated and compared, showing that trapezoidal arrays designs have a higher DC voltage gain while rectangular arrays are more tolerant to process variability. Two new adaptive body bias circuits for CMOS circuits are proposed, which are used to minimize the inverter cells PVT variability and at the same time control the push–pull based OTAs common mode output voltage and transconductance. A schematic-level simulation of a hybrid Nauta–Vieru OTA prototype was run and achieved as result a differential voltage gain of 58 dB, a CMRR of 108 dB, a total power consumption of 375 nW, unity gain-bandwidth product of 100 kHz for a capacitive load of 10 pF, and a total area of 13,650 \(\upmu \hbox {m}^2\). The same OTA was fabricated and its DC transfer functions were measured, showing a maximum 52 dB voltage gain, 73 dB CMRR and \(11~\upmu \hbox {V/A}\) transconductance at a 0.5 V voltage supply.

中文翻译：

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基于推挽运算的跨导放大器拓扑，用于超低压电源

摘要

这项工作提出了一种基于Nauta和Vieru的基于推挽OTA的共模抑制性能得到改善的运算跨导放大器，该器件在180 nm CMOS工艺中在0.5 V电源下工作，另外还有一个采用自适应体偏置技术的偏置电路输出共模电压的校准。仿真和比较了由矩形和梯形晶体管阵列组成的相等尺寸的CMOS推挽对逆变器单元，这表明梯形阵列设计具有更高的DC电压增益，而矩形阵列更能容忍工艺变化。提出了两种新的用于CMOS电路的自适应体偏置电路，这些电路用于最大程度地减小逆变器单元PVT的可变性，并同时控制基于推挽式OTA的共模输出电压和跨导。 \（\ upmu \ hbox {m} ^ 2 \）。制作了相同的OTA，并测量了其DC传递函数，显示出在0.5 V电压下的最大52 dB电压增益，73 dB CMRR和（11〜\ umu \ hbox {V / A} \）跨导。