贾天宇 - 北京大学 - 集成电路学院

个人简介

教育背景： 2015.9-2019.12，美国西北大学，计算机工程，博士 2015.9-2018.12，美国西北大学，计算机工程，硕士 2011.9-2014.3，北京邮电大学，硕士 2007.9-2011.6，北京邮电大学，学士工作经历： 2022.1-至今，北京大学，助理教授 2021.8-2021.12，美国卡耐基梅隆大学，助理研究教授 2020.3-2021.7，美国哈佛大学，博士后

研究领域

新型人工智能加速器芯片设计系统集成SoC芯片设计与优化可重构与可编程AI芯片架构研究超低功耗数字电路设计

近期论文

查看导师新发文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

1.Tianyu Jia et al., A 12nm agile-designed SoC for swarm-based perception with heterogeneous IP Blocks, a reconfigurable memory hierarchy, and an 800MHz multi-plane NoC, IEEE 48th European Solid-State Circuits Conference (ESSCIRC), Sep. 2022. 2.Tianyu Jia et al., NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance, International Symposium on Microarchitecture (MICRO), Oct. 2020. 3.Tianyu Jia et al., A compute-adaptive elastic clock chain technique with dynamic timing enhancement for 2D PE array based accelerators, International Solid-State Circuits Conference (ISSCC), Feb. 2020. 4.Tianyu Jia et al., An adaptive clock scheme exploiting instruction-based dynamic timing slack for a GPGPU architecture, IEEE Journal of Solid-State Circuits (JSSC), 2020. 5.Tianyu Jia et al., A dynamic timing enhanced DNN accelerator with compute-adaptive elastic clock chain technique, IEEE Journal of Solid-State Circuits (JSSC), 2020. 6.Tianyu Jia et al., An adaptive clock management scheme exploiting instruction-based dynamic timing slack for general-purpose graphic processor unit with deep pipeline and out-of-order execution, International Solid-State Circuits Conference (ISSCC), Feb. 2019.