近期论文
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Zhaoxuan Dong, Aijiao Cui*, Hao Lu, "Non-invasive Reverse Engineering of One-hot Finite State Machines using Scan Dump Data" IEEE Transactions on emerging topics in computing, Oct, 2023, accepted. (IF = 5.9, JCR 1区)
Aijiao Cui, Zhen Weng, Hui Zhang, Gang Qu, Huawei Li," SATAM: A SAT attack resistant resistant active metering against IC overbuilding," IEEE Transactions on emerging topics in computing, vol. 10, No. 4, 2022, pp. 2025-2041. (IF = 6.6, JCR 1区)
Aijiao Cui*, Chengkang He, C. H. Chang, H. Lu, " Identification of FSM State Registers by Analytics of Scan-dump data," IEEE Transactions on Information Forensics and Security, vol. 11, Nov. 2021, pp. 5138-5153. (IF = 7.2, JCR 1区，CCF-A类期刊)
Aijiao Cui*, C. H. Chang, W. Zhou, Y. Zheng,"A New PUF Based Lock and Key Solution for Secure In-field Testing of Cryptographic Chips", IEEE Transactions on emerging topics in computing, vol. 9, no. 2, April 2021, pp. 1095-1105. ( IF = 6.6, JCR 1区)
Aijiao Cui*, M. Li, G. Q, H. Li, "A Guaranteed Secure Scan Design based on Test Data Obfuscation by Cryptographic Hash", IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 39, no. 12, Dec. 2020,pp. 4524-4536 (IF = 2.6, JCR 2区， CCF-A类期刊)
Aijiao Cui*, Y. Luo and C. H. Chang,"Static and dynamic obfuscation of scan data against scan-based side-channel attacks" IEEE Transactions on Information Forensics and Security, vol. 12, no. 2, Feb. 2017, pp. 363-376. (IF = 7.2, JCR 1区，CCF-A类期刊)
Aijiao Cui*, Yanhui Luo, Huawei Li, Gang Qu,"Why current secure scan design fail and how to fix them" Integration, the VLSI Journal, 56 (2017), pp. 105-114. (IF =1.3，JCR3区，CCF-C类期刊)
Aijiao Cui*, G. Qu and Y. Zhang,"Ultra-low overhead dynamic watermarking on scan design for hard IP protection" IEEE Transactions on Information Forensics and Security, vol.10, no.11, July 2015, pp. 2298-2313. (IF = 7.2, JCR 1区， CCF-A类期刊)
L. Chen, Aijiao Cui* and C. H. Chang,"Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction" IEEE Transactions on Computers, vol. 64, no. 12, Feb. 2015, pp. 3417-3492. (IF = 3.2, JCR 2区， CCF-A类期刊 )
R. Sun, Y. Zhang and A. Cui,"a refined affine approximation method of multiplication for range analysis in word-length optimization" Eurasip Journal on Advances in Signal Processing, March 2014, article 36. (IF=1.8, JCR 3区)
Aijiao Cui*, C. H. Chang and S. Tahar, “A robust FSM watermarking scheme for IP protection of sequential circuit design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,vol. 30, no. 5, May 2011, pp. 678-690. (IF = 2.6, JCR 2区，CCF-A类期刊)
C. H. Chang and Aijiao Cui, “Synthesis-for-Testability watermarking for field authentication of VLSI intellectual property,” IEEE Trans. on Circuits and Systems I, vol. 57, no. 7, August 2010，pp. 1618-1630.(SCI检索，影响因子4.1, JCR 2区 )
Aijiao Cui, C. H. Chang and S. Tahar, “IP watermarking using incremental technology mapping at logic synthesis level,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 9, Sept. 2008, pp. 1565-1570. (IF = 2.6, JCR 2区，CCF-A类期刊)
侯建军，佟毅，崔爱娇，曾涛，数字电路实验一体化教程（2003年高等教育百门精品课程教材建设立项项目），清华大学出版社、北京交通大学出版社，2007年1月。
会议论文及发表演说
Omid Aramoon, Gang Qu, Aijiao Cui, "building hardware security primitives using scan-based design-for-testability" in 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), invited talk, Aug. 2022, pp. 1-6.
Mengqiang Lu, Aijiao Cui*, Yan Shao, Gang Qu, "A Memristor-base Secure Scan Design against the Scan-based Side-Channel Attacks" in 2022 on Great Lakes Symposium on VLSI, Sept. 2022, pp. 71-76. (CCF-C类会议）
Qidong Wang, Aijiao Cui, Gang Qu, "Identification of counter registers through full scan chain," in International test conference-Asia, Aug. 2021, pp. 1-5. (CCF-C类会议）
Zhenxing Chang, Aijiao Cui*, Ziming Wang, Gang Qu, "Novel memristor-based nonvolatile D latch and flip-flop designs", 2021 International Symposium on Quality Electronic Design (ISQED), pp, 244-251, April 2021
Zhichao Xu, Aijiao Cui*, Gang Qu, "A new aging sensor for the detection of recycled ICs" in GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI, Sept. 2020, pp. 223-228. (CCF-C类会议）
Ziming Wang, Aijiao Cui, Gang Qu,"A low-cost fault injection attack resilient FSM design" in 2020 IEEE 33rd International System-on-Chip Conference (SOCC), pp.19-24, Sept. 2020. Best paper award.
Aijiao Cui*, Yuxi Wang, " How to retrieve PUF response from a fabricated chip securely?” in 2020 International Symposium on Quality Electronic Design (ISQED), March 2020, p 21-26.
Qidong Wang, Aijiao Cui*, G. Qu and H. Li, “A New Secure Scan Design with PUF-based Key for Authentication”, in 2020 IEEE VLSI Test Symposium, April 2020, accepted.(CCF-C类会议)
Chengkang He, Aijiao Cui*, Chiphong Chang, “Identification of State Registers of FSM Through Full Scan by Data Analytics” in 2019 IEEE Asian HOST, Dec. 2019, best paper candidate.
Aijiao Cui*, Zhenxing Chang, Ziming Wang, Gang Qu, Huawei Li "A memristor-based scan hold flip-flop" in Proceedings IEEE Non-Volatile Memory Systems and Applications Symposium, August, 2019, pp. 1-2.
Peiqi Sun, Aijiao Cui*, "A new pay-per-use scheme for the protection of FPGA IP" in Proceedings IEEE International Symposium on Circuits and Systems, May 2019, pp. 1-5. (CCF-C类会议)
Aijiao Cui*, Yan Yang, Gang Qu, Huawei Li, "A secure and low-overhead active IC metering scheme" in IEEE VLSI Test Symposium, April 2019, pp. 1-6. (CCF-C类会议)
Aijiao Cui*, Wei Zhou, Gang Qu, Huawei Li, "A new scheme to extract PUF information by scan chain", in proceedings IEEE Asian Test Symposium, Oct. 2018, pp. 104-108. (CCF-C类会议)
Xi Chen, Zhaojun Lu, Gang Qu, Aijiao Cui, "Partial scan design against scan-based side channel attacks," in 2018 IEEE TrustCom/BigDataSE, pp. 1481-1489. (CCF-C类会议）
Xi Chen, Omid Aramoon, Gang Qu, Aijiao Cui, "Balancing testability and security by configurable partial scan design" in International test conference-Asia, Aug. 2018, pp. 145-150. (CCF-C类会议）
Wenxuan Wang, Aijiao Cui*, Gang Qu, Huawei Li, “A Low-overhead PUF based on Parallel Scan Design” in Proceedings Asia and South Pacific Design Automation Conference ASP-DAC 2018, Jan. 2018, pp. 715-720. (CCF-C类会议)
Wei Zhou, Aijiao Cui*, Huawei Li, Gang Qu, “How to secure scan design against scan-based side-channel attacks?” in proceedings IEEE Asian Test Symposium, Nov. 2017, invited paper, pp. 121-126. (CCF-C类会议)
Aijiao Cui*, Xuesen Qian, Gang Qu, Huawei Li, “A New Active IC metering Technique based on Locking Scan Cells” In proceedings IEEE Asian Test Symposium, Nov. 2017, pp. 40-45. (CCF-C类会议)
Xiaonan Huang, Aijiao Cui*, Chip Hong Chang," A New Watermarking Scheme on Scan Chain Ordering for Hard IP Protection" in Proceedings IEEE International Symposium on Circuits and Systems, May 2017, pp. 1-4. (CCF-C类会议)
X. Chen, G. Qu, Aijiao Cui, "Practical IP watermarking and fingerprinting methods for ASIC designs" 2017 IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, pp: 1-4.(CCF-C类会议)
X. Chen, G. Qu, Aijiao Cui, C. Dunbar, "Scan chain based IP fingerprint and identification" in 2017 18th International Symposium on Quality Electronic Design (ISQED), 2017, pp: 264 - 270.
Jiadong Wang, Aijiao Cui*, Mengyang Li, Gang Qu and Huawei Li,"An ultra-low overhead LUT-based PUF for FPGA" in Proceedings IEEE Asian HOST, Dec. 2016, pp. 1-6.
Yanhui Luo, Aijiao Cui*, G. Qu and Huawei Li," A new countermeasure against scan-based side-channel attacks," in Proceedings IEEE International Symposium on Circuits and Systems, May 2016, pp. 1722-1725. (CCF-C类会议)
Lucheng He, Aijiao Cui*," An improved test power optimization method by insertion of linear function," in Proceedings IEEE International Symposium on Circuits and Systems, May 2016, pp. 2631-2634. (CCF-C类会议)
Aijiao Cui, T. Yu, M. Li and G. Qu,"A scan design method based on two complementary connection styles to minimize Test power" in Proceedings IEEE International Symposium on Circuits and Systems, May 2015, pp. 625-628. (CCF-C类会议)
Aijiao Cui, T. Yu, G. Qu and M. Li,"An improved scan design for minimization of test power under routing constraint" in Proceedings IEEE International Symposium on Circuits and Systems, May 2015, pp. 629-632. (CCF-C类会议)
T. Yu, Aijiao Cui, M. Li, A. Ivanov,"A new decompressor with ordered parallel scan design for reduction of test data and test time" in Proceedings IEEE International Symposium on Circuits and Systems, May 2015, pp. 641-644. (CCF-C类会议)
M. Gao, K. Lai, J. Zhang, G. Qu, Aijiao Cui, Q. Zhou ,"Reliable and anti-cloning PUFs based on configurable ring oscillators" in International conference on computer-aided design and computer graphics, April 2015, pp. 194-201.
M. Li, Aijiao Cui and T. Yu,"An Improved Scan Cell Ordering Method Using the Scan Cells with Complementary Outputs" in Proceedings 14th International Symposium on Integrated Circuits, Dec. 2014, pp. 103-106. (CCF-C类会议)
T. Yu, Aijiao Cui and M. Li, "A new scan ordering method for test power optimization under routing constraint" in IEEE 15th Workshop on RTL and High Level Testing, Nov. 2014.
Aijiao Cui, W. Liang and G. Qu,"A low-overhead dynamic watermarking scheme on scan design for easy authentication" in Proceedings IEEE International Symposium on Circuits and Systems, June 2014, Melbourne, Australia, pp. 778-781. (CCF-C类会议)
Y. Liu, Aijiao Cui,"An efficient zero-aliasing space compactor based on elementary gates" on proceedings of 2013 13th International Conference on Computer-Aided Design and Computer Graphics, Hongkong, Nov. 2013, pp. 95-100.
L. Chen and Aijiao Cui, “A power-efficient scan tree design by exploring the Q'-D connection,” in Proceedings IEEE International Symposium on Circuits and Systems, Beijing, China, May 2013, pp. 1018-1021. (CCF-C类会议)
Aijiao Cui, and C. H. Chang, “A Post-processing scan-chain watermarking scheme for VLSI intellectual property protection” in Proceedings IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, Taiwan, pp. 412-415, Dec. 2012.
Aijiao Cui, C. H. Chang and L. Zhang, “A hybrid watermarking scheme for sequential functions,” in Proceedings IEEE International Symposium on Circuits and Systems, Rio. Brazil, pp. 2333-2336, May 2011. (CCF-C类会议)
Aijiao Cui and C. H. Chang, “An improved publicly detectable watermarking scheme based on scan chain ordering,” Proc. IEEE Int. Symp. on Circuits and Syst., Taipei, May 2009, pp. 29-32. (CCF-C类会议)
Aijiao Cui and C. H. Chang, “Intellectual property authentication by watermarking scan chain in design-for-testability flow,” Proc. IEEE Int. Symp. on Circuits and Syst., Seattle, USA, May 2008, pp. 2645-2648. (CCF-C类会议)
Aijiao Cui and C. H. Chang, “Watermarking for IP Protection through Template Substitution at Logic Synthesis Level,” Proc. IEEE Int. Symp. on Circuits and Syst., New Orleans, USA, May 2007, pp. 3687-3690. (CCF-C类会议)
Aijiao Cui and C. H. Chang, “Kernel Extraction for Watermarking Combinational Logic Networks,” Proceedings IEEE Asia Pacific Conference on Circuits and Systems, Singapore, December 2006, pp. 1023-1026.
Aijiao Cui and C. H. Chang, “Stego-signature at logic synthesis level for digital design IP protection,” Proceedings IEEE International Symposium on circuits and Systems, Kos, Greece, May 2006, pp. 4611-4614. (CCF-C类会议)
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