Breaking the subthreshold slope limit in MOSFETs
Introduction
The active search of sharper-switching devices is motivated by the urgent need to lower the operating voltage and energy consumption without compromising the current drive capability. Many device concepts have been proposed without being adopted by industry. Tunneling transistors do not show much progress, ferroelectric FETs are still under development and NEMS seem inappropriate for high-density logic [1]. Only the band-modulation devices exhibit experimentally abrupt switching but they are double-body PIN diodes with miniaturization limitations [2]. This context consolidates the reign of the MOSFET and justifies the attempts to get the best of it.
It is the subthreshold slope that defines the transition between OFF and ON states. We consider long transistors operated in the ohmic region such as to avoid velocity and current saturation or self-heating. In a bulk or partially-depleted SOI MOSFET, the swing SS (inverse of the slope) is [3]
where Cit = qDit is the capacitance associated with the interface trap density Dit. Suppressing the large value of the depletion capacitance Cd was a good reason to switch to fully-depleted transistors. The swing is indeed much lower in double-gate MOSFETs such as FinFETs [4]
and in FD-SOI [5]where Csi, Cbox and Citb are the capacitances of the depleted silicon film, buried dielectric (BOX) and back-interface traps, respectively. In ultrathin FD-SOI transistors with low interface trap density SSFD ≈ SSDG. The short-channel effects are responsible for higher swing values.
Even though the impact of traps is drastically reduced thanks to the technology evolution and the implementation of extremely thin dielectrics (Cox ≫ Cit), the barrier of 2.3kT/q subsists. It is often called “Boltzmann tyranny” [6], [7], because it blocks the subthreshold swing to a minimum level of 60 mV/decade at room temperature. This simplistic allegation, omnipresent in the literature, is more a rule of thumb rather than a physical law. We show that its foundation is incorrect due to confusion between mobile charge and current.
While the theoretical limit of 2.3 kT/q per decade is incontestable, the crucial question is: Per decade of what: mobile charge or drain current?
Section snippets
Theory and experimental background
We all know that the inversion charge Qinv is related to the surface potential ψs through Boltzmann’s statistics as Qinv ∼ exp(qψs/kT). The variation of the charge with gate voltage VG can be written as:where n = dVG/dψs ≥ 1 is the capacitive body factor. Being device-dependent, its formulation reduces to one of the parentheses of Eqs. (1–3). In other words, the subthreshold swing in Eqs. (1–3) describes the variation of the inversion charge with gate
Simulations and discussion
Numerical simulations have been conducted for a long FD-SOI transistor with 10-nm-thick body, 2.5 nm gate oxide and 150 nm BOX. The charge was computed with the Lambert function model and the mobility with Eq. (7). Fig. 3a shows the mobility behavior which is very sensitive to the amount of potential fluctuations. The corresponding transfer characteristics ID (VG) are presented in Fig. 3b. For large potential fluctuations, a double slope develops in the subthreshold region near VG = 0.35 V
Conclusion
In deep subthreshold regime, the carrier transport is severely altered by potential fluctuations and Coulomb scattering centers. Both mechanisms are attenuated by the screening effect produced by the increasing mobile charge density. Multiple experiments reveal a massive improvement of the carrier mobility from weak to strong inversion. This mobility boost makes the current increase faster than the inversion charge. The theoretical minimum swing of 2.3kT/q limits the charge variation but does
Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
References (24)
- et al.
Analytical expressions for subthreshold swing in FDSOI MOS structures
Solid-State Electron
(2018) - et al.
Differential magnetoresistance technique for mobility extraction in ultra-short channel FDSOI transistors
Solid-State Electron
(2006) - et al.
Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique
Solid-State Electron
(2007) - et al.
Low temperature characterization of mobility in 14 nm FD-SOI CMOS devices under interface coupling conditions
Solid-State Electron
(2015) - et al.
Modeling inversion-layer carrier mobilities in all regions of MOSFET operation
Solid-State Electron
(2002) - et al.
Electron mobility in heavily doped junctionless nanowire SOI MOSFETs
Microelectron Eng
(2013) - et al.
A review of sharp-switching devices for ultra-low power applications
J Electron Device Society
(2016) - et al.
A review of sharp-switching band-modulation devices
Micromachines
(2021) - Y. Taur and T.H. Ning, Fundamentals Modern VLSI Devices, 3rd ed., New York, NY, USA: Cambridge Univ. Press, 2021. DOI:...
- S. Cristoloveanu, Fully Depleted Silicon-On-Insulator: Nanodevices, Mechanisms and Characterization. Amsterdam, The...
Steep-slope hysteresis-free negative capacitance MoS2 transistors
Nat Nanotechnol
An all two-dimensional vertical heterostructure graphene/CuInP 2 S 6 /MoS 2 for negative capacitance field effect transistor
Nanotechnology
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