Capture and emission time map to investigate the positive VTH shift in p-GaN power HEMTs☆
Introduction
GaN-based HEMTs are emerging as a competitive solution for high-efficiency power converters, able to deliver high power in smaller form factors, compared to their silicon counterpart [1]. Despite the recent development, GaN is a relatively young material, whose potential has still to be fully exploited. Therefore, the ability to investigate, understand, and describe charge trapping processes in GaN devices becomes of primary importance to propel the development of this technology.
In the framework of power electronics applications, normally off operation is highly desirable. An attractive method to achieve enhancement mode devices is the use of a p-doped layer under the gate area [2], to lift the vertical band diagram to higher energies, such that the 2DEG depletion occurs even in the absence of an applied external bias. A Schottky contact at the metal/p-GaN junction can be used to mitigate the leakage through the p-i-n junction formed between the p-GaN layer and the channel [3]. However, this creates a back-to-back diode configuration between the metal/p-GaN and the p-GaN/AlGaN/GaN diodes.
The potential at the internal node controls the charge density in the channel, but its potential strongly depends on the leakage through the two diodes in series, which depends on material defectiveness, thus complicating the analysis [4]. Additionally, unstable operations, such as threshold voltage instability during the on-phase have been widely observed [5].
Within this paper, a detailed analysis of threshold voltage instability under positive gate voltage stress in p-GaN power HEMTs is presented. First, the stability of the devices under test (DUTs) is assessed by means of pulsed IV characterization. Then, for the first time we use the capture and emission time (CET) map approach [6] to investigate and describe the charge trapping processes within the devices, allowing the identification of the energetic signature of the capture and emission processes, and of the related physical model.
Section snippets
Device description and DC measurements
The devices under test (DUTs) are 100 V rated E-mode power GaN-on-Si HEMTs with a Schottky p-GaN gate with source field plate, C-doped buffer, and gate width W = 100 μm.
The growth of III-N layers has been carried out by using metalorganic chemical vapor deposition (MOCVD) on 200 mm Si (111) wafers. The epi-stack consists of a 200-nm AlN nucleation layer, a 0.33-μm (Al) GaN superlattice layer combined with a 0.5-μm C-doped GaN back barrier [7], a 200-nm undoped GaN channel layer, an AlGaN
CET map extraction
To gain further insight on the PBTI in our devices, we investigated the capture and emission time constant distribution of the observed VTH shift. Ideally, the trapping phenomena originate from single defects, and a de-trapping transient should show a pure exponential trend; however, it has been widely shown that this rarely happens in real devices [10].
Recently, the CET map approach has been proposed as a useful technique to reveal extended defects in the Al2O3 gate oxide and ionization of
Conclusion
Within this paper, for the first time we investigated the negative charge trapping processes of GaN HEMTs by means of combined pulsed-IV measurements and CET map analysis.
The results provide a clear description of the temperature-dependence of the trapping and de-trapping process, supporting the hypothesis that threshold voltage shift originates from the trapping of electrons from the channel to traps in the AlGaN barrier, located 0.10 eV above the conduction band of GaN; de-trapping dominated
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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2023, Microelectronics ReliabilityReview and Outlook on GaN and SiC Power Devices: Industrial State-of-the-Art, Applications, and Perspectives
2024, IEEE Transactions on Electron DevicesOn the CET-Map Ill-Posed Inversion Problem: Theory and Application to GaN HEMTs
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2023, IEEE Transactions on Electron Devices
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This activity was supported by project iRel40. iRel40 is a European co-funded innovation project that has been granted by the ECSEL Joint Undertaking (JU) under grant agreement No 876659. The funding of the project comes from the Horizon 2020 research program and participating countries. National funding is provided by Germany, including the Free States of Saxony and Thuringia, Austria, Belgium, Finland, France, Italy, the Netherlands, Slovakia, Spain, Sweden, and Turkey. This project is co-funded by the Ministry of Economic Development in Italy.