Robust resistive switching characteristics of AlOx CBRAM using simple and cost-effective thermal evaporation process

https://doi.org/10.1016/j.microrel.2022.114765Get rights and content

Highlights

  • Aluminium oxide based CBRAM stack explored for data storage

  • Annealing of the device shows substantial improvement in memory performance.

  • Thermal evaporation method used for dielectric deposition as low cost option

  • Annealed device shows good repeatability, DC and pulse endurance as well as memory window.

  • Unannealed devices did not follow the Weibull statistic, requiring cluster model to be applied.

Abstract

In this study, we have reported improved CBRAM device performance using a simple fabrication process consisting of thermal evaporation and metal annealing. The fabricated and annealed Al/Cu/AlOx/TiN CBRAM shows 600 consecutive DC cycles of switching at 200 μA with a high ON/OFF ratio of >260, P/E endurance of >1.5 × 108 cycles with 100 ns pulse widths and very stable retention life in LRS at 1.2 V and 1.3 V for >4000 s. Annealing enhances AlOx surface morphology, which results in controlled copper migration, improving the resistive switching properties, especially for the LRS state. Furthermore, the statistical analysis of switching data using the Weibull distribution confirms lower variability for the annealed device due to controlled copper migration.

Introduction

Conducting bridge random access memory (CBRAM) or electrochemical metallization cell (EMC) as it is commonly referred to, is an essential candidate for the next-generation non-volatile memories due to its features including simple metal-insulator-metal (MIM) structure, high switching speed (ns), excellent scalability, robustness to harsh end use applications and relatively low operating voltages [1], [2]. Chemically active metals like Cu and Ag are used as active top electrodes (TE) in CBRAM structures, and chemically inert materials like W, TiN, Pt, Au, etc., are used for the bottom electrode (BE) in the MIM stack [3], [4]. Several oxide materials such as HfO2 [5] Al2O3 [6], Ta2O5 [7], TiNxOy [8] MoS2 [9], etc., have been extensively explored for CBRAM device fabrication in the past.

Excellent CMOS compatibility, high thermal stability, large energy bandgap (>7 eV), moderately high dielectric constant, low Gibbs free energy of formation (−1582.3 kJ/mole), simple device integration, and cost-effectiveness make AlOx an ideal dielectric media or switching layer (SL) for resistive switching and conductive filament formation. [10], [11]. Generally, the quality of resistive switching performance depends very much on the material deposition technique [4], interface/buffer engineering [8], [9], [10], [11], [12], multilayer structures [13] and several other device design factors. In general, atomic layer deposition (ALD) and sputter deposition techniques are extensively used to deposit AlOx switching materials as it stabilizes the surface morphology of the materials [14]. Although these deposition techniques improve the uniformity of the deposited materials, they are quite expensive for commercial electronics applications.

This article proposes a thermally fabricated Cu (TE) and AlOx (SL) based CBRAM structure. The as-fabricated devices show very high non-uniformity in resistive switching properties. Hence, to improve the resistive switching of the CBRAM, another set of devices have been fabricated and annealed using post metallization annealing (PMA) at 400 °C in an N2 ambient for 10 min. Annealing enhances AlOx surface morphology and atomic uniformity [15], significantly improving the CBRAM device's resistive switching. Memory characteristics of both unannealed and annealed devices are compared here. The use of the thermal evaporation method and the thermal metal annealing process is the essential novelty of this study. It is a cost-effective process to improve the resistive switching characteristics. Statistical analysis is also performed using Weibull plots to assess the variability in switching trends for the two sets of devices.

The paper is organized as follows. Section 2 explains the device fabrication process and electrical characterization test details. The DC and AC endurance characteristics of the CBRAM device, its switching and retention trends as well as statistical analysis of switching data using Weibull plots are all discussed in several subsections of Section 3. Finally, the outcomes of the study and future work plans are summarized in Section 4.

Section snippets

Fabrication process

A 200 nm thick SiO2 layer was initially deposited on a Si substrate using a dry oxidation process. Following that, 200 nm thick Ti layer and 40 nm TiN as a bottom electrode were deposited sequentially. Then, a 150 nm thick SiO2 layer was deposited. The via-hole pattern was created using a standard photolithography process, and device sizes of 1 × 1 μm2 were obtained. Subsequently, 4 nm aluminium (Al) (which will oxidize to form AlOx as a switching material (SM)) was deposited by the thermal

Characterization of CBRAM devices

The CBRAM device schematic is shown in Fig. 2(a). Two devices were fabricated with an AlOx thickness of 4 nm each. One of the devices is unannealed, while the other is annealed in PMA, and their memory characteristics are examined.

Conclusions of the study

We have shown a remarkable improvement in resistive switching properties of the CBRAM device fabricated using cost-effective thermal evaporation and PMA at 400 °C for 10 min in an N2 ambient. The annealed devices show superior performance metrics with 600 consecutive DC cycles at 200 μA with a memory window of >260 and a highly stable LRS state with P/E endurance of >1.5 × 108 cycles. Retention tests in the LRS state point to a very robust filament in the annealed device which remained

CRediT authorship contribution statement

Anirudha Deogaonkar: Conceptualization, Formal Analysis, Device Characterization, Modeling, Analysis and Validation, Visualization, Writing - Original draft preparation.

Mainak Seal - Investigation and Data Visualization, Device Characterization, Discussions, Analysis.

Asim Senapati: Device Fabrication.

Sreekanth Ginnaram: Device Fabrication.

Alok Ranjan: Physical Device and Materials Characterization, Discussions, Analysis.

Siddheswar Maikap: Supervision. Project administration, Funding acquisition.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgements

This work was supported by the Ministry of Science and Technology, Taiwan (MOST) under contract number: MOST-108-2221-E-182-026. The authors are grateful to EOSL/ITRI, Hsinchu, Taiwan for supporting the patterning of the wafers. The corresponding author would like to acknowledge the financial and logistical support from the A*STAR BRENAIC Research Project No. A18A5b0056, which enabled the characterization and device analyses to be accomplished.

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