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A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal

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Abstract

Frequency agility has been extensively used in military and commercial-communication applications due to its inherent transmission security features. This paper proposes algorithms and system-level design to intercept as well as monitor of frequency-agile signal in real-time by receiver. Receiver is assumed to have no prior knowledge of spread spectrum hopping sequence used by the frequency agile transmitter. Novelty of design is capability of simultaneously & reliably intercepting multiple frequency-agile transmissions with signal-to-noise ratio (SNR) requirement of 15dB, whereas other interceptor needs minimum SNR of 30 dB Pan et al. (IEEE Transactions on Signal Processing, 23(5):1113–1122, 1) and monitoring of intercepted transmitter upto message bits/audio level in real time. Unlike the conventional approach, this technique is independent of number of transmitters and is designed to achieve higher throughput. Additionally, it mitigates the storage requirement or memory for recording the entire spread bandwidth while intercepting and monitoring the frequency-agile signal off-the-shelf. The proposed system has been designed to process frequency-agile signal with instantaneous frequency-band ranging from 13 MHz to 31 MHz with the hop-rate of 100 hops/second. Hardware prototype of this system has been implemented on a Virtex-7 FPGA platform with 22% resource occupancy and 1.667 W of total power consumption. Subsequently, we have tested this FPGA prototype using the real-world signals with the aid of 16-bit on-board ADC, digital oscilloscope, spectrum analyzer and signal generator that produce signals of 10 hopping frequencies (21, 30, 15, 25, 31, 18, 19, 17, 29 & 13 MHz) with a hopping time of 10 msec. Finally, the performance analysis of this system has been carried out to observe the variations of the parameters like processing latency, tracker resolution and percentage of correct hop-estimation with respect to the BER.

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Authors and Affiliations

  1. Defence Research and Development Organization (DRDO), Ministry of Defence, Government of India, New Delhi, India

    Lalit Kumar

  2. School of Computing and Electrical Engineering, Indian Institute of Technology Mandi, Himachal Pradesh, 175005, India

    Rahul Shrestha

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  1. Lalit Kumar
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  2. Rahul Shrestha
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Correspondence to Rahul Shrestha.

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Kumar, L., Shrestha, R. A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal. J Sign Process Syst 94, 1395–1410 (2022). https://doi.org/10.1007/s11265-022-01810-2

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