Capacitive probing of electronic phase separation in an oxide two-dimensional electron system

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Capacitive probing of electronic phase separation in an oxide two-dimensional electron system

Sander Smink, Hans Boschker, Alexander Brinkman, Jochen Mannhart, and Hans Hilgenkamp

Phys. Rev. B 106, 054205 – Published 15 August 2022

Abstract

Interfaces between specific complex oxides host two-dimensional electron systems (2DESs) with strong electron-electron interactions. This combination yields a rich phenomenology, including an apparently intrinsic electronic phase separation (EPS). We designed an experiment to study the origins and magnitude of EPS in oxide 2DESs in more detail. We measure the capacitance between the 2DES at the ${LaAlO}_{3} / {SrTiO}_{3}$ interface and an electrode on top of the ${LaAlO}_{3}$ as a function of applied gate voltage. Our measurements reveal a significant reduction of this capacitance in the region of the phase diagram where the charge-carrier density is low. The tunnel conductance is reduced as well, which implies that part of the interface becomes insulating. These measurements allow us to directly estimate the magnitude of the EPS at a carrier density of several $10^{13} {cm}^{- 2}$ , higher than the nominal carrier density in most experiments. The pattern in the capacitance-voltage measurements reflecting the local metal-insulator transitions suggests that the main driver for EPS is a strong variation of the electrostatic potential with a non-normal probability distribution. We study the effect of this in-plane potential variation on the electronic properties of the 2DES by mapping the full superconducting dome as a function of both backgate and topgate voltage. This map shows that, once insulating patches emerge, the global critical temperature $T_{c}$ falls, while the onset temperature—i.e., highest local $T_{c}$ —remains fairly constant.

Received 1 June 2022
Revised 25 July 2022
Accepted 28 July 2022

DOI:https://doi.org/10.1103/PhysRevB.106.054205

Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI. Open access publication funded by the Max Planck Society.

Published by the American Physical Society

Physics Subject Headings (PhySH)

Capacitance Electronic phase separation Metal-insulator transition Superconducting phase transition Superconductor-insulator transition

Two-dimensional electron system

Resistivity measurements

Condensed Matter, Materials & Applied Physics

Authors & Affiliations

Sander Smink ^1,2, Hans Boschker¹, Alexander Brinkman ², Jochen Mannhart¹, and Hans Hilgenkamp²

¹Max Planck Institute for Solid State Research, Heisenbergstraße 1, 70569 Stuttgart, Germany
²MESA+ Institute for Nanotechnology, University of Twente, P. O. Box 217, 7500 AE Enschede, The Netherlands

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Issue

Vol. 106, Iss. 5 — 1 August 2022

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Images

Figure 1
Experimental setup. (a) Optical micrograph of a completed device. Labels indicate the electrical connections for the in-plane measurements and for the topgate voltage. (b) Schematic cross section across the device along the red, dashed line in (a). The connections for the topgate voltage $V_{T}$ and backgate voltage $V_{B}$ are indicated, along with the sourced ac input voltage $U_{in}$ , the measured ac output voltage $U_{out}$ , and the measured ac input current $I_{in}$ . The arrows illustrate the electric field $E$ induced by applying a positive $V_{T}$ or $V_{B}$ . Layer thicknesses and lateral dimensions not to scale. (c) Equivalent circuit for out-of-plane transport following the two-port method [56]. It consists of $N$ equal elements, in which a capacitance $C_{p} / N$ is connected in parallel to a conductance $G_{p} / N$ . A series resistance $R_{s} / N$ connects to the next element. The limit of $N \to \infty$ has an exact solution.
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Figure 2
Electrostatic tuning of the capacitance measured between the topgate electrode and the interface $C_{p}$ . (a) Map of $C_{p}$ as a function of backgate voltage $V_{B}$ and topgate voltage $V_{T}$ . Data taken at $T = 30 mK$ . (b) Corresponding map of the derivative of $C_{p}$ with respect to $V_{B}$ . This plot highlights three distinct regions of capacitance tuning by the gate voltages, indicated by the roman numerals.
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Figure 3
Correspondence of the capacitance $C_{p}$ (blue circles) and the tunnel conductance $G_{p}$ (orange squares) measured between the topgate electrode and the interface, as a function of the backgate voltage $V_{B}$ . $T = 30 mK$ . In all curves, $C_{p}$ and $G_{p}$ are normalized to their respective values at $V_{B} = + 180 V$ . The topgate voltage $V_{T}$ was fixed at different values during the measurements, which are indicated by the labels printed above the respective curves. For clarity, the curves are offset vertically by 0.2.
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Figure 4
Electrostatic tuning of the superconducting transition as a function of temperature. (a) Sheet resistance $R_{sheet}$ measured as a function of temperature $T$ . Between subsequent curves, the backgate voltage $V_{B}$ increases in steps of 20 V. (b) $R_{sheet}$ as a function of $T$ for a varying topgate voltage $V_{T}$ , which increases in steps of 50 mV between curves. (c) Onset temperature $T_{c, onset}$ (orange circles) and zero-resistance temperature $T_{c, 0}$ (blue squares) as a function of $V_{B}$ . Lines are guides to the eye. (d) $T_{c, onset}$ and $T_{c, 0}$ as a function of $V_{T}$ . The red shading in the background depicts the magnitude of the measured dc gate leakage current as a function of $V_{T}$ .
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Figure 5
Tuning the superconducting critical temperatures by a combined application of backgate voltage $V_{B}$ and topgate voltage $V_{T}$ . (a) Tuning of the zero-resistance temperature $T_{c, 0}$ . The main panel on the bottom left shows $T_{c, 0}$ on a color scale—given on the top right—as a function of both gate voltages. In the white-shaded area, the resistance was nonzero always for $T \geq 20 mK$ . The top panel shows $T_{c, 0}$ as a function of $V_{B}$ for various fixed values of $V_{T}$ . These curves represent horizontal line cuts across the main panel between between the orange ( $V_{T} = 0.1 V$ ), blue ( $V_{T} = 0.3 V$ ), and dark red ( $V_{T} = 0.5 V$ ) triangles. The panel on the right-hand side shows $T_{c, 0}$ as a function of $V_{T}$ for various fixed values of $V_{B}$ . These curves represent vertical line cuts across the main panel, between the olive ( $V_{B} = - 100 V$ ), violet ( $V_{B} = 0 V$ ), and gray ( $V_{B} = + 100 V$ ) triangles. The red shading represents the magnitude of the dc gate leakage current. Lines connecting data points are guides to the eye. (b) Same as (a), mapping the onset temperature $T_{c, onset}$ as a function of both gate voltages. In the white areas of the main panel, no superconducting onset could be detected in the measurements.
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