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CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors

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Abstract

Approximate computing is one of the emerging concepts in multimedia applications like image processing applications. In the research world, it is getting more attention from researchers. Because of sacrificing a smaller scale in the accuracy of the design, it reduces the circuit parameters like area complexity, delay, and power. The purpose of this work is to survey the Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementation of modified Dadda multiplier architecture using various approximate 4:2 compressor designs presented for the last few decades. Based on implementation outcomes, this survey examines the approximate modified Dadda multiplier design performance for its closeness to the exact computation. In addition, the comparison is carried out based on approximate 4:2 compressors performance, an error rate of the particular design, the accuracy analysis metrics of approximate multiplier and its area utilization, power consumption, and delay.

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Data Availability Statement

Data sharing not applicable to this article as no datasets were generated or analysed during the current study.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, K.Ramakrishnan College of Technology, Samayapuram, Trichy, Tamil Nadu, 621112, India

    Parthibaraj Anguraj & Thiruvenkadam Krishnan

  2. Department of Electronics and Communication Engineering, K. S. Rangasamy College of Technology, Tamil Nadu, 637215, Namakkal, India

    Saravanan Subramanian

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  1. Parthibaraj Anguraj
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  2. Thiruvenkadam Krishnan
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  3. Saravanan Subramanian
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Correspondence to Parthibaraj Anguraj or Thiruvenkadam Krishnan.

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Anguraj, P., Krishnan, T. & Subramanian, S. CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors. J Electron Test 38, 353–370 (2022). https://doi.org/10.1007/s10836-022-06010-1

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