Low Area FPGA Implementation of AES Architecture with EPRNG for IoT Application

Abstract

Nowadays, the Internet of Things (IoT) is widely used in the daily lives of humans, which range from tiny wearable devices to huge industrial systems. However, designing the IoT application is difficult, because the devices in the IoT network are susceptible to security threats (e.g. malicious attacks). Therefore, an effective cryptographic process must be developed with a minimum amount of hardware resources. In this paper, an optimized Advanced Encryption Standard (AES) architecture is proposed to improve the security between the IoT devices. The following key strategies are involved in the proposed AES architecture: 1) Efficient Pseudo Random Number Generator (EPRNG) using the two-level True Random Number Generator based key generation module is used to generate a different optimal key value for each clock cycle, 2) the number of logical elements used in the AES architecture is minimized because there is no registers are required for storing the generated keys as it is automatic key generation. The performances of the EPRNG-AES architecture are analyzed in terms of the number of slice registers, flip flops, number of slice Look Up Table (LUT), number of logical elements, slices, bonded Input/ Output Block (IOB), power, delay, and operating frequency. The EPRNG-AES architecture is evaluated with five different AES architectures such as AES-PNSG, LAES, AES-HLS, AES-CTR and AES-MMC. The EPRNG-AES architecture designed in the Kintex 7 uses 153 slices, which is less when compared with the number of slices in LAES and AES-HLS.