Abstract
CMOS technology scaling allows the design of even more complex system but, at the same time, introduces some reliability problems. In particular, aggressively scaled microelectronic technologies are affected by the Bias Temperature Instability (BTI) aging phenomenon that results in an increase of the absolute value of the transistor threshold voltage with aging time and a consequent reduction for the microelectronic circuit reliability. In this paper we estimate the performance degradation caused by BTI on an operational amplifier (OPAMP) in open loop configuration as well as on three other analog amplifiers based on OPAMPs. The results have shown that BTI can seriously impact the performance of the investigated circuits, and that such performance degradation worsens as operating temperature increases. We also briefly describe a possible low-cost monitoring scheme to detect the performance degradation of the OPAMPs caused by BTI. The effectiveness of our monitor has been validated by means of pre-layout electrical simulations, and the results have shown that it can be reliably used to evaluate the OPAMPs aging degradation.
Similar content being viewed by others
Data Availability
Data are available on request from the authors.
References
Agarwal M, Balakrishnan V, Bhuyan A, Kim K, Paul BC, Wang W, Yang B, Cao Y, Mitra S (2008) Optimized Circuit Failure Prediction for Aging: Practicality and Promise. Proc. of IEEE International Test Conference 1–10
Alam MA, Mahapatra S (2005) A Comprehensive Model of PMOS NBTI Degradation. Microelectron Reliab 45(1):71–81
Alam MA, Kufluoglu H, Varghese D, Mahapatra S (2007) A comprehensive model for PMOS NBTI degradation: Recent progress. Microelectron Reliab 47:853–862
Cabrera-López J, Romero-Beltrán C (2014) Auto-adjustable low-signal processing technique based on programmable mixed-signal. SoCs Proc. of 9th Ibero American Congress on Sensors 1–4
Copetti T, Medeiros GC, Poehls LB, Vargas F (2016) NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time. J Electron Test 32(3):315–328
Davidović V, Danković D, Golubović S, Djorić-Veljković S, Manić I, Prijić Z, Prijić A, Stojadinović N, Stanković S (2018) NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs. Facta Universitatis, Series: Electronics and Energetics 31(3):367–388
Danković D, Manić I, Davidović V, Djorić-Veljković S, Golubović S, Stojadinović N (2008) Negative Bias Temperature Instability in n-Channel Power VDMOSFETs. Microelectron Reliab 48 (8–9):1313–1317
Fukui M, Nakai S, Miki H, Tsukiyama S (2011) A dependable power grid optimization algorithm considering nbti timing degradation. Proc. of IEEE Interantional New Circuits and Systems Conference 370–373
Grossi M, Omaña M (2019) Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers. J Electron Test 35(2):261–267
Hao-I Wei Hwang Y, Chuang Ching-Te (2011) Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High- \kappa Metal-Gate Devices. IEEE Transactions on in Very Large Scale Integration (VLSI) Systems 19(7):1192–1204
Huard V, Denais M (2004) Hole Trapping Effect on Methodology for DC and AC Negative Bias Temperature Instability Measurements in PMOS Transistors. Proc of IEEE International Reliability Physics Symposium 40–45
Jha NK, Reddy PS, Sharma DK, Rao VR (2005) NBTI Degradation and Its Impact forAnalog Circuit Reliability. IEEE Trans Electron Devices 52(12):2609–2615
Joshi K, Mukhopadhyay S, Goel N, Mahapatra S (2012) A consistent physical framework for N and P BTI in HKMG MOSFETs Proc. of IEEE International Reliability Physics Symposium (IRPS) 15–19
Keane J, Kim T-H, Kim CH (2009) An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation. IEEE Transactions. on Very Large Scale Integration Systems 18(6):947–956
Mahato S, De Wit P, Maricau E, Gielen G (2012) Offset Measurement Method for Accurate Characterization of BTI-Induced Degradation in Opamps. Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) 661–664
Maricau E, Gielen G (2011) Transistor Aging-Induced Degradation of Analog Circuits: Impact Analysis and Design Guidelines. Proc. of IEEE European Conference on Solid-State Circuits (ESSCIRC) 243–246
Martins MT, Medeiros GC, Copetti T, Vargas FL, Poehls LB (2017) Analysing NBTI Impact on SRAMs with Resistive Defects. J Electron Test 33(5):637–655
Omaña M, Rossi D, Edara T, Metra C (2016) Impact of Aging Phenomena on Latches’ Robustness. IEEE Trans Nanotechnol 15(2):129–136
Predictive Technology Model ASU http://ptm.asu.edu/
Rossi D, Cazeaux JM, Omaña M, Metra C, Chatterjee A (2009) Accurate Linear Model for SET Critical Charge Estimation. IEEE Transactions on VLSI Systems 17(8):1161–1166
Rossi D, Tenentes V, Reddy SM, Al-Hashimi BM, Brown A (2017) Exploiting aging benefits for the design of reliable drowsy cache memories. IEEE Trans Comput Aided Des Integr Circuits Syst 37(7):1345–1357
Taghipour S, Asli RN (2019) Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops. J Electron Test 35(1):119–125
Tahanout C, Tahi H, Djezzar B, Benabdelmomene A, Goudjil M, Nadji B (2014) An accurate combination of on-the-fly interface trap and threshold voltage methods for NBTI degradation extraction. J Electron Test 30(4):415–423
Toledano-Luque M, Kaczer B, Franco J, Roussel J, Grasser T, Hoffmann TY, Groeseneken G (2011) From Mean Values to Distribution of BTI Lifetime of Deeply Scaled FETs Through Atomistic Understanding of the Degradation. Proc. of Symposium on VLSI Technology, Digest of Technical Papers 152–153
Usmani F, Hasan M (2009) Design and Parametric Analysis of 32nm OPAMP in CMOS and CNFET Technologies for Optimum Performance. Proc. of IEEE Argentine School of Micro-Nanoelectronics, Technology and Applications 87-92
Wan J, Kerkhoff H (2011) Boosted gain programmable Opamp with embedded gain monitor for dependable. SoCs, Proc. of IEEE International SoC Design Conference 294 – 297
Wang W, Wei Z, Yang S, Cao Y (2007) An Efficient Method to Identify Critical Gates under Circuit Aging Proc of IEEE/ACM International Conference on Computer-Aided Design 735–740
Weste N, Harris D (2004) CMOS VLSI Design A Circuits and Systems Perspective. Addison-Wesley, New York
Yu Y, Liang J, Yang Z, Peng X (2018) NBTI and power reduction using a workload-aware supply voltage assignment approach. J Electron Test 34(1):27–41
Acknowledgments
The Authors would like to thank to Mr. F. Nazari and Mr. S. Lottante for their help in the preliminary simulations that have been conducted for the analysis described in this paper.
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: M. Sachdev.
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Grossi, M., Omaña, M. Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers. J Electron Test 37, 533–544 (2021). https://doi.org/10.1007/s10836-021-05967-9
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-021-05967-9