Use of passive, quantitative EBIC to characterize device turn-on in 7 nm technology

https://doi.org/10.1016/j.microrel.2021.114380Get rights and content

Abstract

A novel analysis routine is proposed that visualizes the opening of a transistor channel using Electron Beam Induced Current (EBIC) with a net zero-volt bias across a channel. nFET devices on a 7 nm technology node chip were examined in two different regions of the sample. With varying gate voltage, the device turn-on was clearly evident in the resulting EBIC image. Quantitative analysis of the resulting currents is demonstrated, and shows the channel opening up at voltages earlier than shown by I-V measurement. A mechanism for this difference is proposed. The analysis, also involving a 2-dimensional map of the space, provides opportunities for detecting regional variations in the electrical properties or performance at the high resolutions afforded with a scanning electron microscope (SEM).

Section snippets

Motivation for work

Successful yield engineering of semiconductor processing requires the ability to locate defects and characterize devices. With increasing device density due to advancing technology nodes, the need for failure analysis to detect subtle defects and subtle device variations becomes even more critical. Nanoprobing and its attendant localization techniques are becoming an increasingly important part of these analytical workflows. Also increasing with shrinking technology nodes is the sensitivity of

Basic concepts and demonstration of need

Two electron-based techniques are increasingly useful for characterization of devices which have been delayered to contact level and will be discussed in this paper. Electron Beam Induced Current (EBIC) and Electron Beam Absorbed Current (EBAC) [1], [2] are techniques which measure the current arriving at a probe tip, correlated to the positional scanning of an electron beam of a Scanning Electron Microscope (SEM). If the sample were to have no internal electric fields, the technique merely

Procedure and results

A commercially available 7 nm technology sample was delayered to contact level, and a logic area of the chip was examined using various nanoprobing techniques. Two nFET transistors from different regions were examined in detail.

Fig. 3 shows the nanoprobing setup. The left image shows the SEI image while the right image shows a transistor's family of curves. There is considerable increase in source-to-drain current at gate voltages between 0.3 V and 0.4 V. The positive gate voltage turns the

Quantitative results and discussion

The EBIC analysis software provides the ability not only to map the currents pictorially by means of contrast, but also to graph the numerical values across a series of line scans. A quantitative analysis was undertaken for Region 2. Fig. 9 demonstrates the typical placement of the line scan box, which was 20 pixels wide and 700 pixels long (about 380 nm).

Fig. 10 shows a graph of these current data, where each point is the 20-pixels average across the scan. This seemingly extreme length of line

Summary of mechanisms

It would now be helpful to review the proposed mechanisms for each case. First of all for the case of gate turned off, the result is simply the EBAC of contact that was probed. Fig. 13 explains this simplistic result.

Next it would be useful to review the possible phenomena at play for the gate-on scenario. Fig. 14 highlights three possible sources or drivers of current in the sample. To be considered are: a) secondary electron emission b) depletion zones, and c) the Seebeck effect. Of these

Conclusions

A novel method for non-destructive evaluation of device turn-on has been demonstrated on 7 nm technology logic devices. The method uses no applied voltage across source and drain and therefore may be capable of isolating phenomena which might be clouded by such confounding mechanisms as drain-induced barrier lowering, etc. There is much less current flowing across the channel, and thus a device may be able to withstand longer or more elaborate analysis before being adversely affected. The

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

References (8)

  • E. Cole

    Beam-Based Defect Localization Techniques

    (2007)
  • B. Buchea et al.

    High Resolution Electron Beam Induced Resistance Change for Fault Isolation With 100nm2 Localization

    (2016)
  • G. Johnson et al.

    Electron Beam Induced Resistance Change for Device Characterization and Defect Localization

    (2016)
  • J. Phang

    A Review of Laser Induced Techniques for Microelectronic Failure Analysis

    (2004)
There are more references available in the full text version of this article.

Cited by (3)

View full text
© 2021 Published by Elsevier Ltd.