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A Novel Nanoscale SOI MOSFET by Using a P-N Junction and an Electrically Hole Free Region to Improve the Electrical Characteristics

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Abstract

In this paper, a SOI MOSFET is proposed using a P-N structure and an electrically hole-free region (EHFR-SOI). In this structure, to improve the electrical characteristics such as short channel effects, self-heating effects, and floating body effects, a Si3N4 layer is used on the source side of the SOI MOSFET with a P-N structure. The proposed technique converts the P-N structure to a N-P-N structure by creating an electrically hole-free region. So, by reducing the applied electric field to the carriers, a significant reduction in the electron temperature of the device will be created. Simulations and studies of the structure show that its thermal behavior is significantly improved. Also, the floating body effect, effective mobility, hot electron effect, and electric field in the structure are enhanced compared to a conventional SOI (C-SOI) structure. In addition, the gate-source and gate-drain capacitors have been improved, which indicates a higher switching speed of the structure.

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Data Availability

The data that support the findings of this study are available from the authors, upon reasonable request.

References

  1. Plößl A, Kräuter G (2000) Silicon-on-insulator: materials aspects and applications. Solid State Electron 44(5):775–782

    Article  Google Scholar 

  2. Veeraraghavan S, Fossum J (1989) Short-channel effects in SOI MOSFETs. IEEE Trans Electron Devices 36(3):522–528

    Article  Google Scholar 

  3. Zareiee M, Mehrad M (2017) A reliable nano device with appropriate performance in high temperatures. ECS J Solid State Sci Technol 6(4):M50

    Article  CAS  Google Scholar 

  4. Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans Device Mater Reliab 4(1):99–109

    Article  Google Scholar 

  5. Fukuda Y, Ito S, Ito M (2001) SOI-CMOS device technology. OKI Tech Rev 4:54

    Google Scholar 

  6. Park H, Colinge JP, Cristoloveanu S, Bawedin M (2020) Persistent floating-body effects in fully depleted silicon-on-insulator transistors. Physica Status Solidi (A) 217(9):1900948

    Article  CAS  Google Scholar 

  7. Colinge J (2008) The new generation of SOI MOSFETs. Rom J Inf Sci Technol 11(1):3–15

    Google Scholar 

  8. Singh RK, Saxena A, Rastogi M (2011) Silicon on insulator technology review. Int J Eng Sci Emerging Technol 1(1):1–16

    CAS  Google Scholar 

  9. Mishra VK, Rao N (2020) Electrostatic investigation of intended source drain ultra thin body FD-SOI MOSFET. Silicon pp. 1–9

  10. Muthuseenu K, Barnaby HJ, Patadia A, Holbert K, Privat A (2020) Ionizing radiation tolerance of stacked Si3N4-SiO2 gate insulators for power MOSFETs. Microelectron Reliab 104:113554

    Article  CAS  Google Scholar 

  11. Ramezani Z, Orouji AA (2019) An asymmetric nanoscale SOI MOSFET by means of a PN structure as virtual Hole’s well at the source side. Silicon 11(2):761–773

    Article  CAS  Google Scholar 

  12. Shaik RR, Arun G, Chandrasekar L, Pradhan  KP (2020) A study of workfunction variation in pocket doped FD-SOI technology towards temperature analysis. Silicon pp. 1–10

  13. Tahne BA, Naderi A, Heirani F (2020) Reduction in self-heating effect of SOI MOSFETs by three vertical 4H-SiC layers in the BOX. Silicon 12(4):975–986

    Article  CAS  Google Scholar 

  14. Kononchuk O, Nguyen BY (2014) Silicon-on-insulator (soi) technology: manufacture and applications. Elsevier

  15. Verma S, Abdullah M (2015) Review of SOI MOSFET design and fabrication parameters and its electrical characteristics. Int J Comput Appl 130(17):1

    CAS  Google Scholar 

  16. Anvarifard MK, Orouji AA (2013) Improvement of self-heating effect in a novel nanoscale SOI MOSFET with undoped region: a comprehensive investigation on DC and AC operations. Superlattice Microst 60:561–579

    Article  CAS  Google Scholar 

  17. Rahimian M, Orouji AA (2012) A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect. Mater Sci Semicond Process 15:445–454

    Article  CAS  Google Scholar 

  18. Gritsenko VA, Perevalov TV, Islamov DR (2016) Electronic properties of hafnium oxide: a contribution from defects and traps. Phys Rep 613:1–20

    Article  CAS  Google Scholar 

  19. Ramezani Z, Orouji AA (2017) Amended electric field distribution: a reliable technique for electrical performance improvement in nano scale SOI MOSFETs. J Electron Mater 46(4):2269–2281

    Article  CAS  Google Scholar 

  20. Mehrad M, Zareiee M (2016) Improved device performance in nano scale transistor: an extended drain SOI MOSFET. ECS J Solid State Sci Technol 5(7):M74

    Article  CAS  Google Scholar 

  21. Karbalaei M, Dideban D (2016) A novel silicon on insulator MOSFET with an embedded heat pass path and source side channel doping. Superlattice Microst 90:53–67

    Article  CAS  Google Scholar 

  22. Mehrad M (2021) Inserting different charge regions in power MOSFET for achieving high performance of the electrical parameters. Silicon 13(4):1107–1111

    Article  CAS  Google Scholar 

  23. Triantopoulos K, Cassé M, Barraud S, Haendler S, Vincent E, Vinet M, Ghibaudo G (2019) Self-heating effect in FDSOI transistors down to cryogenic operation at 4.2 K. IEEE Trans Electron Devices 66:3498–3505

    Article  CAS  Google Scholar 

  24. Ghaffari M, Orouji AA (2018) A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect. Superlattice Microst 118:61–78

    Article  CAS  Google Scholar 

  25. Zareiee M (2017) High performance nano device with reduced short channel effects in high temperature applications. ECS J Solid State Sci Technol vol. 6(7)

  26. Anvarifard MK, Orouji AA (2018) Proper electrostatic modulation of electric field in a reliable nano-SOI with a developed channel. IEEE Trans Electron Devices 65(4):1653–1657

    Article  CAS  Google Scholar 

  27. Kamal AK, Singh J (2020) Simulation-based ultralow energy and high-speed LIF neuron using silicon bipolar impact ionization MOSFET for spiking neural networks. IEEE Trans Electron Devices 67(6):2600–2606

    Article  CAS  Google Scholar 

  28. Zareiee M (2019) A new architecture of the dual gate transistor for the analog and digital applications. AEU-Int J Electron Commun 100:114–118

    Article  Google Scholar 

  29. Hanaei M, Orouji AA, Ramezani Z, Amiri IS (2020) A silicon on nothing LDMOS with two air pillars in gate insulator for power applications. Silicon 12:2581–2586

    Article  CAS  Google Scholar 

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The authors received no financial support for the research, authorship, and/or publication of this article.

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Authors and Affiliations

  1. Electrical and Computer Engineering Department, Semnan University, Semnan, Iran

    S. Amir Bozorgi, Ali A. Orouji & Abdollah Abbasi

Authors
  1. S. Amir Bozorgi
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  2. Ali A. Orouji
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  3. Abdollah Abbasi
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Contributions

S. Amir Bozorgi: Conceptualization, Writing – original draft, Software.

Ali A. Orouji: Supervision – review & editing.

Abdollah Abbasi: Validation, review & editing.

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Correspondence to Ali A. Orouji.

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Bozorgi, S.A., Orouji, A.A. & Abbasi, A. A Novel Nanoscale SOI MOSFET by Using a P-N Junction and an Electrically Hole Free Region to Improve the Electrical Characteristics. Silicon 14, 5905–5912 (2022). https://doi.org/10.1007/s12633-021-01304-z

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