Efficient partial product reduction for image processing application using approximate 4:2 compressor
Abstract
Purpose
This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.
Design/methodology/approach
The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block.
Findings
Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs.
Originality/value
The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.
Keywords
Acknowledgements
The authors are willing to express gratitude towards all staff of Digital Electronics Lab, Department of Electronics and Communication engineering, NIT Meghalaya for providing the necessary resources for the research. The authors also wish to thank the Indian Government for providing financial support under Device Development Program (DDP) (Grant No. - DST/TDT/DDP-27/2018).
Citation
Kattekola, N., Jawale, A., Nath, P.K. and Majumdar, S. (2021), "Efficient partial product reduction for image processing application using approximate 4:2 compressor", Circuit World, Vol. ahead-of-print No. ahead-of-print. https://doi.org/10.1108/CW-09-2020-0220
Publisher
:Emerald Publishing Limited
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