Abstract
In this paper, we propose a new technique in silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor in order to obtain a high breakdown voltage. The structure is characterized by multiple N and P doped wells (diode wells) in the buried oxide. Therefore, we call the structure multiple diode wells SOI LDMOS (MDW-LDMOS). The key idea in this work is to amend the electric field of the buried oxide layer and modulate the electric field in the drift region, both of them leading to a high breakdown voltage. Based on the electric displacement continuity, the charge densities in the wells effectively amend the electric field of the buried oxide layer and reduce the electric field of the silicon layer. Also, the diode wells make the uniform distribution of the electric field by producing multiple additional peaks. Using two-dimensional numerical simulation, we demonstrate that the breakdown voltage of the proposed structure improves about 260% in comparison with a conventional LDMOS (C-LDMOS) structure.
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References
Anvarifard MK, Ramezani Z, Amiri IS, Nejad AM (2020) A nanoscale-modified band energy junctionless transistor with considerable progress on the electrical and frequency issue. Mater Sci Semicond Process 107(2019):104849
Guo J, Hu S, Guo G, Liu C, Yang H (2020) Results in physics reducing specific on-resistance for a trench SOI LDMOS with L-shaped P / N pillars. Results Phys 18(July):103254
Mehrad M (2021) Inserting different charge regions in power MOSFET for achieving high performance of the electrical parameters. Silicon 13(4):1107–1111
Erlbacher T (2014) Lateral power transistors in integrated circuits. Springer
Ramezani Z, Orouji AA (2018) A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects. Int J Electron 105(3):361–374
Anvarifard MK (2017) An impressive structure containing triple trenches for RF power performance ( TT-SOI-MESFET ). J Comput Electron 17(1):230–237
Mehrad M (2016) Omega shape channel LDMOS: a novel structure for high voltage applications. Phys E Low-Dimensional Syst Nanostruct 75:196–201
Wang Y, Wang Z, Bai T, Kuo JB (2018) Modeling of breakdown voltage for SOI trench LDMOS device based on conformal mapping. IEEE Trans Electron Devices 65(3):1056–1062
Wang Y, Duan B, Sun L, Yang X, Huang Y, Yang Y (2021) Breakdown point transfer theory for Si/SiC heterojunction LDMOS with deep drain region. Superlattices Microstruct 151(December 2020):106810
Zareiee M (2019a) A new structure for lateral double diffused MOSFET to control the breakdown voltage and the on-resistance. Silicon 11(6):3011–3019
Dong Z, Duan B, Fu C, Guo H, Cao Z, Yang Y (2018) Novel LDMOS optimizing lateral and vertical electric field to improve breakdown voltage by multi-ring technology. IEEE Electron Device Lett 39(9):1358–1361. https://doi.org/10.1109/LED.2018.2854417
Hanaei M, Orouji AA, Ramezani Z, Amiri IS (2020) A silicon on nothing LDMOS with two air pillars in gate insulator for power applications. Silicon 12(11):2581–2586
Wu L, Chen J, Yang H, Ding Q, Chen X, Su S (2021) A ultra - low specific on - resistance and extended gate SJ LDMOS structure. Trans Electr Electron Mater 0123456789. https://doi.org/10.1007/s42341-021-00302-7
Gavoshani A, Orouji AA, Abbasi A (2021) A novel deep gate LDMOS structure using double P-trench to improve the breakdown voltage and the on-state resistance. Silicon:1–6. https://doi.org/10.1007/s12633-020-00857-9
Saadat A, Put M, Edwards H, Vandenberghe WG (2020) Channel length optimization for planar LDMOS field-effect transistors for low-voltage. IEEE J Electron Dev Soc 8(June):711–715
Mehrad M, Zareiee M, Orouji AA, Member S (2017) Controlled kink effect in a novel high-voltage LDMOS transistor by creating local minimum in energy band diagram. IEEE Trans Electron Dev 64(10):4213–4218
Zareiee M (2019b) A novel dual trench gate power device by effective drift region structure. Superlattice Microst 125:8–15
Appels JA, Vaes HMJ (1979) High voltage thin layer devices (Resurf devices). Adv Chem Ser:238–242. https://doi.org/10.1109/IEDM.1979.189589
Weibe J, Matthus C, Schlichting H, Mitlehner H, Erlbacher T (2020) RESURF n- LDMOS transistor for advanced integrated circuits in 4H-SiC. IEEE Trans Electron Dev 67(8):3278–3284
Gavoshani A, Orouji AA (2021) A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature. J Comput Electron 20(4):1513–1519
Orouji AA, Pak A (2015) Numerical simulation of lateral diffused metal oxide semiconductor field effect transistors : a novel technique for electric field control to improve breakdown voltage. Mater Sci Semicond Process 34:230–235
Orouji AA, Moghadam HA, Dideban A (2010) Double window partial SOI- LDMOSFET: a novel device for breakdown voltage improvement. Phys E Low-Dimensional Syst Nanostruct 43(1):498–502
Mehrad M, Orouji AA, Taheri M (2015) Materials science in semiconductor processing a new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature. Mater Sci Semicond Process 34:276–280
Jamali Mahabadi SE, Orouji AA, Keshavarzi P, Moghadam HA (2011) A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage. Semicond Sci Technol 26(9)
Zareiee M, Orouji AA, Mehrad M (2016) A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region. J Comput Electron 15(2):611–618
Device Simulator ATLAS, Silvaco, International, (2012). www.silvaco.com
Atlas User’s Manual, Santa Clara, CA: Silvaco International, (2016). www.silvaco.com
Cristoloveanu S (2001) Silicon on insulator technologies and devices : from present to future. Solid State Electron 45:1403–1411
Luo X, Zhang B, Li Z, Guo Y, Tang X, Liu Y (2007) A novel 700-V SOI LDMOS with double-sided trench. IEEE Electron Dev Lett. 28(5):422–424
Mehrad M, Orouji AA (2013) Superlattices and Microstructures Injected charges in partial SOI LDMOSFETs : A new technique for improving the breakdown voltage. Superlattices Microstruct 57(2013):77–84
Luo X, Zhang B, Li Z (2008) New high-voltage (> 1200 V) MOSFET with the charge trenches on partial SOI. IEEE Trans Electron Dev 55(7):1756–1761
Mansoori HA, Orouji AA, Dideban A (2017) New technique to extend the vertical depletion region at SOI-LDMOSFETs. J Comput Electron 16(3):666–675
Singh Y, Punetha M (2013) A lateral trench dual gate power MOSFET on thin SOI for improved performance. ECS J Solid State Sci Technol 2(7):113–117
Fan Y et al (2014) An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement. J Semicond 35(3):1–6
Pak A, Orouji AA (2016) A novel technique at LDMOSs to improve the figure of merit. Superlattice Microst 93:11–17
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A. Gavoshani: Conceptualization, Writing -original draft, Software.
M. Dehghan: Conceptualization, Software.
Ali A. Orouji: Supervision - review & editing.
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Gavoshani, A., Dehghan, M. & Orouji, A.A. A New Technique to Improve Breakdown Voltage of SOI LDMOSs: Multiple Diode Wells. Silicon 14, 5801–5808 (2022). https://doi.org/10.1007/s12633-021-01354-3
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DOI: https://doi.org/10.1007/s12633-021-01354-3