An adaptive core mapping algorithm on NoC for future heterogeneous system-on-chip
Introduction
In the development of high-performance parallel processors, multiprocessing chips (MPSoC) play a crucial role. In recent years, the processor industry's fundamental design aims to accomplish well-executed output by avoiding parallelism. The System-on-Chip (SoC) is nothing but different processor cores integrated into a single chip [1]. The correspondence formats, which commonly utilized as a part of current SoCs, are bus-based. It understood that a bus data processing capacity shared by all processors attached to it, so its processor size cannot determine it. Secondly, when expanding the number of cores, a reduction in frequency is experienced, and at the same time, the power consumption increases.
Further, SoCs permit a single system to communicate at a time. The configuration of the corresponding communication infrastructure becomes crucial. Network-on-Chip (NoC) was familiarized in chip design to make it capable of communication characteristics like flexibility and performance [2]. It is a new outlining feature found among SoCs. In NoC, different cores (Processing elements) connect to the routers via Network Interface (NI). The network utilizes the packet-switched on-chip communication among the cores, which maintains a high versatility, re-usability, and parallelism in communication. As per the ongoing trend, the number of cores embedded on a network gets increased exponentially. It becomes a significant challenge to execute the tasks of an application in less period, which also leads to low performance. The core mapping strategy was used to solve this problem by determining the easiest way to complete the application tasks. The research work [3] clearly explained the various application mapping mechanisms and their importance.
This paper proposes an Adaptive Core Mapping (ACM) technique, which contains two steps. The first one is mapping the cores according to the application, and the second one is spare core placement. Suppose a fault occurs at any core after mapping; in that case, the fault diagnostic approach used to assess the position of the damaged resource and correct the error using error detection and correction mechanisms (this refers to transient/intermittent faults). If the faults occur even after applying the fault diagnosis method (it means permanent faults), perform task migration using spare core placement. The proposed technique is better in terms of average delay, throughput, and energy consumption when compared to related algorithms. In this research, the Noxim simulator used for the network simulation revised to support different routing algorithms. The proposed adaptive core mapping algorithm is synthesized and simulated using Vivado Design Suite 2018.3 and verified on the Kintex-7 FPGA KC705 board. Results obtained show that the proposed algorithm has improved performance, area reduction, and power consumption compared to well-known prior art algorithms.
The organization of sections in the research paper illustrated as follows; Section 2 provides the related works of this research. Section 3 describes the core requirement in NoC platforms. Section 4 contains the proposed methodology. The performance calculation of the proposed technique through Noxim Simulator explained in Section 5. Section 6 discussed the hardware verification of the proposed algorithm, whereas Section 7 provides the conclusion for this research paper.
Section snippets
Related work
The performance improvement has a significant influence on NoC. Trade-offs describe interconnections on-chip architectures implemented for SoCs between delay, throughput, and energy consumption requirements [4]. The 3D IC's contains 3D NoC, which strive for power and performance improvement through microarchitecture parameters [5]. The isolation strategy is embedded in NoC to excel the performance metric, but its complex routing and less consolidation density resulted in more hardware expenses
The core requirement in NoC
A general NoC contains a processing element or core, network interface, and router [11,12]. The data is transferred from one core to another through the network interface and router. The two-dimensional mesh NoC architecture represented in Fig. 1.
Every core present in NoC is associated with a local router via a network interface [13]. In NoC, the cores have distinguished into three types: (1) Regular core, (2) Spare core, and (3) Manager core. The Regular Core processes the task of a given
Proposed core mapping technique
There should be a mechanism to prevent faulty cores from being used in the adaptive core mapping performance evaluation on NoC. The proposed ACM comprises two processes; one is mapping the cores based on application, whereas the other is spare core placement. After mapping the core, if a fault occurs at any core, follow the fault diagnosis method, which determines the location of the damaged resource and correct the error using error detection and correction mechanism. If the faults occur even
Performance evaluation
Noxim simulator used to calculate the performance of proposed Adaptive Core Mapping (ACM). A cyclical-accurate NoC simulator [21] is written in System C and determines the delay, throughput, and energy consumption. The permutation and combination of different inputs in the 6 × 6 NoC platform with the details tabulated, and for each set, a systematic experiment realized on Noxim simulator [22]. A 1-flit packet and 1-flit buffer with a 128-bit channel often used in this analysis, with the channel
Hardware verification
The proposed Adaptive Core Mapping (ACM) is coded in Verilog HDL, synthesized, and simulated in Vivado Design Suite 2018.3. As shown in Fig. 8, FPGA board Kintex-7 (KC705) board is the target device used for synthesis [25]. An FPGA switch acts as input, whereas the LEDs act as output. In the current research, vertices are considered switches, and NoC platform cores are considered LEDs. The faults present in the proposed ACM represented through the switch on board (where *1 denotes no-fault and
Conclusion
The research article presents an adaptive core mapping technique comprising mapping cores and spare core replacement on NoC. The ACM technique showed an increased performance for various sizes of NoC cores. The experiments conducted on 6 × 6 mesh NoCs revealed that the adaptive core mapping technique exhibited greater throughput, lesser delay, and energy consumption than other related algorithms. The current research also addressed the spare core placement issue, which replaces the faulty core
Ethical approval
This article does not contain any studies with human participants or animals performed by any of the authors.
Declaration of Competing Interest
This paper has not communicated anywhere till this moment, now only it is communicated to your esteemed journal for the publication with the knowledge of all co-authors.
Aruru Sai Kumar received B. Tech in Electronics and Communications in 2008 from JNTU Hyderabad, India, and M.Tech in VLSI Design in 2010 from V.I.T University, Vellore, India. He is currently pursuing a Ph.D. in NIT Warangal, India. His research interests focus on Network-on-Chip architecture design, application mapping in 2-D and 3-D environments, and fault-tolerant Network-on-Chip.
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Aruru Sai Kumar received B. Tech in Electronics and Communications in 2008 from JNTU Hyderabad, India, and M.Tech in VLSI Design in 2010 from V.I.T University, Vellore, India. He is currently pursuing a Ph.D. in NIT Warangal, India. His research interests focus on Network-on-Chip architecture design, application mapping in 2-D and 3-D environments, and fault-tolerant Network-on-Chip.
T.V.K Hanumantha Rao received a bachelor of engineering degree in electronics and communication in 1982 from Andhra University, Visakhapatnam, India, and a master's of engineering degree in Integrated Electronics and Circuits in 1984 from IIT Delhi, India. He received his Ph.D. in 2014 from Anna University, Chennai, India. He is currently working as an Associate professor in the Department of Electronics and Communication Engineering in NIT Warangal, India. His research interests focus on BioMedical Signal Processing, fault-tolerant Network-on-Chip, and low power VLSI.
This paper is for special section VSI-rtcc. Reviews processed and recommended for publication by Guest Editor Prof. Sundhararajan.