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Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET)

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Abstract

This paper reports the performance of an epitaxial layer (ETL) based gate modulated (GM-TFET) through 3D Technology Computer Aided Design (TCAD) simulations. The architecture utilizes effects of both vertical tunneling and lateral tunneling phenomena to improve the device performance. Attributes of the ETL, its thickness (tepi) and doping concentration (Nepi) are varied and their impact on device electrical parameters such as transfer characteristic, output performance, subthreshold swing (SS), and threshold voltage (VT) is highlighted. It is observed that both tepi and Nepi significantly influence the different electrical parameters of the ETL based TFET architecture.

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Acknowledgements

The authors acknowledge the funding by Science & Engineering Research Board, Govt. of India (Sanction Reference. No. SRG/2019/000628).

Funding

This work is funded by Science & Engineering Research Board, Govt. of India (Sanction Reference. No. SRG/2019/000628).

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Authors and Affiliations

  1. Department of ECE, Malaviya National Institute of Technology Jaipur, Jaipur, 302017, Rajasthan, India

    Rajesh Saha

  2. School of Electronics, Tezpur University, Napaam, Tezpur, 784028, Assam, India

    Rupam Goswami

  3. Department of ECE, National Institute of Technology Silchar, 788010, Silchar, Assam, India

    Brinda Bhowmick & Srimanta Baishya

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  1. Rajesh Saha
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  2. Rupam Goswami
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  3. Brinda Bhowmick
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  4. Srimanta Baishya
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Contributions

The work and manuscript is written by Rajesh Saha and Rupam Goswami. The grammatical corrections and Figures in this paper have done by Brinda Bhowmick and Srimanta Baishya.

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Correspondence to Rajesh Saha.

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Saha, R., Goswami, R., Bhowmick, B. et al. Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET). Silicon 14, 5713–5718 (2022). https://doi.org/10.1007/s12633-021-01365-0

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