Demonstration of 4H-SiC CMOS circuits consisting of well-balanced n- and p-channel MOSFETs fabricated by ultrahigh-temperature gate oxidation

Silicon carbide (SiC) is the material of choice for next-generation power-electronic devices with high efficiency and high power density. ¹⁾ Following the successful commercialization of SiC-based Schottky barrier diodes (SBDs), full SiC power modules composed of SBDs and metal-oxide-semiconductor field-effect transistors (MOSFETs) are about to expand their field of application. In addition, since the early stages of SiC research, SiC-based complementary MOS (CMOS) integrated circuits have gained attention as emerging electronic devices that can operate in harsh environments. ^2–8) Several digital and analog CMOS circuits, such as inverters, ring oscillators, and operational amplifiers, have been integrated on 6H- and 4H-SiC substrates. The reported SiC-based CMOS circuits have exhibited excellent capability of working at temperatures up to 540 °C ⁶⁾ and superior gamma-irradiation resistance of over 1 MGy. ⁸⁾ However, SiC MOSFETs have suffered from poor MOS interface quality ⁹⁾ and, thus, alternative junction field-effect transistors and metal–semiconductor transistors, which are free from the MOS interface problems, have been explored as alternatives. ^10–14) Nevertheless, SiC-based CMOS technology is expected to offer significant advantages over these alternatives in terms of reduced power dissipation and various circuit applications.

Thermal oxidation of SiC surfaces yields SiO₂ gate dielectric layers in fabricated SiC MOS devices. As for the conventional gate oxidation of 4H-SiC(0001) Si-face surfaces, very low field-effect mobility (μ_FE) was reported for n-channel MOSFETs. ^15,16) Worse still, p-channel SiC MOSFETs with gate oxides formed by conventional thermal oxidation hardly operate, indicating the existence of a huge number of electrical defects at the SiO₂/SiC interfaces, especially near the valence-band edge of 4H-SiC. Although the physical origins of MOS interface defects have not yet been fully clarified, it is known that electrical defects accumulate at the SiO₂/SiC interface with the progress of thermal oxidation ^17,18) and carbon-related defects are the most likely candidate for the dominant interface states near both the conduction and valence band edges of SiC. ^19–21) So far, aiming at development of high-efficiency n-channel SiC MOSFETs, intensive research has been conducted to reduce the interface state density (D_it) near the conduction band edge of 4H-SiC. Various techniques, such as nitridation of the SiO₂/SiC interface, ^22–25) high-temperature hydrogen annealing, ^26,27) and incorporation of phosphorus ²⁸⁾ and alkaline earth metals in the interface, ^29,30) have been investigated as ways of enhancing the performance of n-channel devices. Among them, interface nitridation by high-temperature annealing in NO ambient has been widely adopted for production of SiC MOSFETs. However, the obtained μ_FE of NO-treated devices is still only around 35 cm² V⁻¹ s⁻¹, which is less than the 5% bulk electron mobility of 4H-SiC. ^9,16) Moreover, charge trapping at the nitrided SiO₂/SiC interface, leading to a threshold voltage (V_th) shift, is an essential obstacle to the long-term reliability of SiC MOSFETs. ^31–33) In particular, hole trapping under negative bias stress restricts the maximum allowable oxide field of the NO-treated n-channel devices in practical applications.

Although there are only a few reports on p-channel SiC MOSFETs, modification of SiO₂/SiC interfaces with hydrogen and nitrogen atoms is also beneficial for reducing D_it near the valance band edge. ^34,35) Indeed, the pioneering research on SiC CMOS circuits has been based on these techniques. ^2–8) It should be noted that negative bias stress is continuously applied to the n-channel MOSFETs when the p-channel device is turned on while positive bias stress is applied to the p-channel MOSFETs when the n-channel device is turned on in CMOS circuits. This implies that V_th instability is a serious concern in SiC CMOS technology and that interface modifications with foreign atoms involve a fundamental drawback. Therefore, it is important to find a gate oxidation process that enables well-balanced and highly reliable n- and p-channel SiC MOSFETs without a complex process tuning regardless of the channel type. Recently, we demonstrated that ultrahigh-temperature SiC oxidation in a reduced oxygen partial pressure (O₂/Ar ambient) is effective in reducing carbon impurities at the SiO₂/SiC interfaces. ³⁶⁾ In particular, a significant reduction in D_it near both the conduction and valence band edges was achieved by oxidation at 1600 °C under an oxygen partial pressure of 0.3 kPa, resulting in well-balanced performance of n- and p-channel MOSFETs. ^37–39) Thanks to the pure SiO₂/SiC interface without intentional incorporation of foreign atoms, superior immunity against negative and positive bias stresses have been demonstrated for both n- and p-channel SiC MOSFETs. ^37,39) Furthermore, we confirmed that subsequent post-annealing in H₂/N₂ ambient forming gas annealing (FGA) at high temperatures resulted in a further improvement in device performance. Given this background and our previous achievements, in this study, we used ultrahigh-temperature oxidation and subsequent FGA to fabricate advanced SiC CMOS circuits. The static and dynamic characteristics of discrete n- and p-channel MOSFETs, CMOS inverters, and ring oscillators were investigated to validate the impact of the proposed gate oxidation technique.

As shown in Fig. 1, CMOS inverters [Fig. 1(b)] and 23-stage ring oscillators [Fig. 1(c)] were fabricated on 4° off-axis 4H-SiC(0001) n-type substrates with n-epilayers (doping density: 5 × 10¹⁵ cm⁻³). P-well regions with a depth of about 500 nm and a total dopant density of 5 × 10¹⁶ cm⁻³ (near the surface) were formed by aluminum (Al) ion implantation. Next, Al and phosphorus (P) ion implantations were respectively performed to form box profiles of p⁺ and n⁺ source and drain (S/D) regions with a depth of 200 nm and a total dopant density of 3 × 10²⁰ cm⁻³. All three ion implantations were performed at a substrate temperature of 600 °C with multiple acceleration energies. Activation annealing was conducted at 1600 °C for 5 min in Ar ambient without a capping layer. After growing sacrificial oxides and removing them, gate oxides were grown by a two-step oxidation process for two sets of samples. For both sets, 20 nm thick gate oxides were initially grown at 1300 °C in 100 kPa O₂ ambient followed by ultrahigh-temperature oxidation at 1600 °C in a 0.3 kPa O₂/Ar gas mixture. ^37–39) The resulting oxide thickness was about 30 nm (hereafter called ultrahigh-temperature gate oxidation (HTO)). The second set was subsequently treated with high-temperature FGA at 1200 °C for 30 min (hereafter called FGA). The device fabrication was completed by opening contact holes and evaporating and patterning Al layers to form electrodes and wires. The channel length (L) and width (W) of the n- and p-channel MOSFETs that formed the inverters and ring oscillators were 20 and 150 μm, respectively. Discrete n- and p-channel MOSFETs with a channel length of 100 μm were also fabricated on the same chip to evaluate the individual transistor characteristics. Electrical measurements of the discrete SiC MOSFETs and CMOS inverters were conducted using a semiconductor parameter analyzer (Keysight B1500A). The output waveforms (V_clk) of the 23-stage ring oscillators with a supply voltage (V_DD) were monitored at various temperatures up to 200 °C via a buffer n-channel SiC MOSFET connected to an oscilloscope with a drain-to-source voltage (V_d) of 5 V as shown in Fig. 1(c). The change in the output voltage [V_out in Fig. 1(c)] was monitored by using the oscilloscope while maintaining a constant current (I_ref) through the buffer MOSFET.

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Prior to evaluating the statistic and dynamic performance of the fabricated CMOS circuits, we investigated the discrete n- and p-channel SiC MOSFETs at room temperature. Figure 2(a) shows the normalized drain current versus gate voltage (I_d−V_g) characteristics of the HTO and FGA devices, in which I_d was normalized by the gate length (L), width (W), and oxide capacitance (C_ox) to make a fair comparison. V_d was ±0.1 V for the n- and p-channel devices. Despite the fact that p-channel MOSFETs fabricated by conventional dry oxidation hardly turned on even under large negative V_g conditions (data not shown), the ultrahigh-temperature oxidation and subsequent FGA treatment significantly improved the I_d−V_g characteristics, as it did in our previous study. ³⁹⁾ Judging from the distinct positive V_th shift for the FGA p-channel device with respect with the HTO device, it can be concluded that hole trapping at the SiO₂/SiC interface, which causes a negative V_th shift, was effectively suppressed. This indicates additional defect passivation with hydrogen through the high-temperature FGA in combination with carbon removal by the ultrahigh-temperature oxidation. Also, as shown in Fig. 2(b), the peak values of μ_FE estimated from the I_d−V_g curves of the p-channel HTO and FGA devices are mostly comparable to the previous results. ³⁹⁾ Regarding the n-channel devices, we have reported a threefold μ_FE enhancement by ultrahigh-temperature oxidation compared with the conventional dry oxidation. ³⁷⁾ However, the obtained μ_FE in Fig. 2(b) was below our expectation. As a result, whereas electron mobility in bulk 4H-SiC is much higher than hole mobility, performance of the n-channel MOSFETs is inferior to that of the p-channel one. This is partly due to the higher acceptor density of the p-well region (N_A = 5 × 10¹⁶ cm⁻³) in comparison with the previous study (N_A = 5 × 10¹⁵ cm⁻³). This implies that the performance of n-channel MOSFETs can be further improved by optimizing the acceptor density for the p-well regions, but careful attention should be paid to designing the p-well regions that requires relatively heavy Al dopant atoms in the development of advanced SiC MOS circuits. Nonetheless, it is notable that well-balanced n- and p-channel MOSFETs with mostly symmetric V_th positions and comparable drivability can be realized with a pure SiO₂/SiC interface without interface nitridation by means of the proposed ultrahigh-temperature gate oxidation process.

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Figures 3(a) and 3(b) show voltage transfer curves obtained from the HTO and FGA inverters, in which V_DD was varied from 5 to 15 V and V_in was swept from 0 to V_DD and back to 0 V. Under the low V_DD conditions around 5 V, the HTO device did not exhibit normal inverter operation due to the large ∣V_th∣ for the p-channel MOSFET [less than −10 V as shown in Fig. 2(a)]. When sufficiently high V_DD (over 10 V) was applied to the circuit, the full rail-to-rail output signal and sharp switching behavior were observed for the HTO inverter [Fig. 3(a)]. However, the switching threshold voltage, the point on the transfer curve where V_in = V_out, of the HTO inverter shifted toward the low V_in side with respect to the ideal positions (V_DD/2) indicated by the vertical dotted lines. In addition, the voltage-transfer characteristics (VTC) showed distinct hysteresis at a high V_DD of 15 V. These results are attributable to the relatively large ∣V_th∣ difference between the n- and p-channel HTO MOSFETs [the blue lines in Fig. 2(a)]. In contrast, as shown in Fig. 3(b), the FGA inverter exhibited an ideal threshold voltage (symmetric VTC) and negligible hysteresis under the high V_DD condition, thanks to the well-balanced n- and p-channel FGA MOSFETs [the red lines in Figs. 2(a) and 2(b)]. Furthermore, low-V_DD operation below 10 V could be achievable for the FGA inverter. These results again demonstrate the effectiveness of combined ultrahigh-temperature oxidation and subsequent high-temperature FGA in reducing carrier trapping at the SiO₂/SiC interface.

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Next, the dynamic performance of the SiC CMOS inverters was evaluated by analyzing the output oscillation waveforms of the ring oscillators. Figures 4(a) and 4(b) show the output waveforms of the 23-stage ring oscillators fabricated with HTO and FGA inverters, respectively. The waveforms were acquired by continuously applying V_DD (15 V) and V_d (5 V) at room temperature. Although the circuits were not fully designed to have ideal oscillation waveforms, stable oscillation signals were observed from both circuits. The FGA circuit exhibited a higher oscillation frequency (shorter delay time) as compared with the HTO one because of the enhanced drivability (I_d) and well-balanced V_th for both n- and p-channel MOSFETs due to the effective defect passivation with hydrogen. Moreover, both ring oscillators exhibited stable oscillation in terms of the delay time and waveform for a long period, indicating good immunity against negative and positive bias stresses, as initially expected. The details of the reliability assessment of the inverters and ring oscillators will be described elsewhere.

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Finally, we investigated the stability of the SiC CMOS inverter and ring oscillators at elevated temperatures. Figures 5(a) and 5(b) show the voltage transfer curves of the HTO and FGA inverters measured at V_DD of 15 V. In both cases, the full rail-to-rail output voltage and steep switching behavior were observed even at 200 °C, but the switching threshold voltage shifted toward the lower V_in side, probably due to the asymmetry in V_th between the n- and p-channel MOSFETs. Specifically, whereas the p-channel MOSFETs fabricated by ultrahigh-temperature oxidation and subsequent FGA exhibited a negligible V_th shift up to 200 °C, ³⁹⁾ electron de-trapping from the SiO₂/SiC interface resulted in V_th having a significant temperature dependence in the operation of the n-channel MOSFETs. Nevertheless, the FGA inverter is superior to the HTO one in terms of symmetric operation and hysteresis. Consequently, as shown in Fig. 5(c), the FGA circuit showed a shorter propagation delay as compared with the HTO circuit over the whole temperature range. In both cases, a monotonous decrease in the delay time at high temperatures is due to mobility enhancement of n-channel MOSFETs caused by increased mobile electron density. These results indicate the importance of defect passivation at the SiO₂/SiC interface for stable SiC circuit operation.

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In summary, we successfully demonstrated stable operation of SiC CMOS inverters and ring oscillators consisting of non-nitrided MOS structures. High-quality and pure SiO₂/SiC interfaces offering superior immunity against bias temperature stressing were fabricated by ultrahigh-temperature oxidation and subsequent FGA treatment. A symmetric and steep rail-to-rail VTC of CMOS inverters was realized with the combined method. Furthermore, the dynamic characteristics of the CMOS inverters were evaluated by performing measurements on 23-stage ring oscillators. The results showed the need for well-balanced and reliable MOSFETs in the development of emerging SiC circuits for harsh-environment applications.

Acknowledgments