Optimal calibration of gates in trapped-ion quantum computers

Multiple quantum computing platforms are now publicly accessible and their utility is being actively investigated by a broad community of academia, government, and industry. Trapped-ion quantum computers (TIQCs) have emerged as one of the leading hardware platforms, with well-known advantages in natural qubit replicability and all-to-all qubit connectivity [11, 15, 19, 25]. To now successfully transform a TIQC from an academic demonstration to a commercially viable machine, it becomes critical that the computing system is optimized over a variety of systems engineering metrics, beyond basic requirements, cf [3], such as gate fidelities or control-pulse power requirements.

Viewed through the lens of harnessing the most power out of a TIQC, in this paper, we focus on an important systems engineering metric of reducing the calibration resource requirement. Note that borrowing and adopting common terminologies in conventional computing systems, we distinguish between the user time and system time. User time is the time taken by a TIQC to execute quantum programs, generating economic values by solving quantum computational problems. System time denotes the total time that a TIQC is reserved for and includes time for maintenance and necessary calibrations of quantum gates. Assuming a normal operating condition of a TIQC where minimal physical maintenance or repair is required, for a TIQC to now be a highly profitable machine, it is essential that we minimize the system time used for the upkeep of a TIQC.

Taking a step towards this goal, we aim to find a good set of quantum gates to calibrate for to obtain good fidelities for a batch of input quantum circuits. This way, we can increase the number of quantum computational jobs that are run with an acceptable performance. Note this enables us to defer calibrations that would otherwise be needed for high-fidelity results. We refer to the maximum size of calibration set as budget. Our work aims to maximize the performance of a TIQC for a given budget. This, in turn, also means we can obtain a target performance with a reduced calibration set.

To this end, we propose two heuristics: approximate MCCS (most compact cumulative supergraph (MCCS), see definition 3.3) and genetic algorithms. As we will show later, the problem described above is computationally demanding, rendering the exact solution to be unattainable beyond ∼10 qubits. Thus our heuristics are necessary to obtain scalable, approximate solutions.

Our paper is organized as follows. In section 2, we briefly discuss prior work on optimizing circuits towards a particular quantum hardware architecture. In section 3, we formally introduce our problem of optimizing over calibration resources, along with useful notations and definitions used throughout the paper. In section 4, we present our algorithms, one based on an approximate MCCS finding algorithm and the other based on genetic algorithm. In section 5 we apply our methods to several input circuit batch examples and report our results. We therein further compare our methods to a naive method of random algorithms and benchmark our approaches in their scalability. We discuss our findings in section 6.

The graph theoretic concept that appears frequently in existing literature on optimizing circuit-to-hardware mapping is that of subgraph isomorphism [7]. The use of subgraph isomorphism to optimize circuit-to-hardware mapping has been explored in [12, 14, 21]. Reference [5] uses a token-swapping framework to transform a circuit to a restricted architecture. More recently, mathematical programming tools like satisfiability solvers have been used to find optimal transformations of quantum circuits. References [22, 24] use the Z3 solver [2, 8] to map quantum circuits to architectures offered by IBM and Google.

A vast majority of the approaches discussed above are tailored to quantum computers based on superconductors, which typically have a restricted connectivity limited to, e.g., nearest-neighbor interactions. More importantly, such a restricted architecture demands modification to the circuit in the form of additional SWAP operations. In addition, the approaches listed above try to minimize circuit complexity, i.e., the number of entangling or CNOT gates, and they do not account for the differences in fidelity between individual gates.

Our work differs from the works mentioned above in that, instead of identifying an optimal circuit transformation based on the constraints in underlying hardware, we use the given circuits to calibrate the underlying hardware. This way, we do not introduce any additional gates on the circuits provided, while fully leveraging all-to-all connectivity naturally provided by a trapped-ion quantum computer architecture. This has further importance for commercial quantum computing vendors, since the hardware provider typically is not at liberty to modify the input circuits, provided and specified by a client. Indeed, our experience is that the problem of finding optimal configuration of hardware based on the input circuits is a highly relevant problem for commercial trapped-ion quantum systems.

Our TIQC is specified by a fully-connected graph G_s = (V_s , E_s , ) whose vertices V_s are the qubits of the system. Each edge (i, j) ∈ E_s indicates a connection or a gate between any two qubits i and j. Each edge has an associated infidelity, (i, j), for that gate. Note that the infidelity is a symmetric quantity, i.e., (i, j) = (j, i).

Calibration of an ion-trap system involves selecting a subset of all edges S ⊆ E_s and tuning the hardware parameters to ensure good fidelity of all gates in S. In general, the fidelity of a gate inside S is higher than the fidelity of a gate outside S. Since calibration of gates, which typically requires repeated measurements to collect statistics over a sizable parameter space characterized by the system configuration, is an expensive and time-consuming operation, we aim to reduce the size of S as much as possible.

We assume a model where the ion-trap system undergoes a calibration once for every batch of execution cycles. We consider the batch as a given input, compatible with both the standard practice of first in first out and the optimized batching scenario, wherein the similarity between the batched circuits, to be concretely discussed later, is maximized by a careful selection process. Specifically, let $\mathcal{C}=\left\{{c}_{i}\right\}$ be the batch of quantum circuits that are run per calibration sequence. A quantum circuit $c\in \mathcal{C}$ (hereafter dropping the element index i for notational brevity) has a graph representation G_c = (V_c , E_c , w) where V_c represents logical-level, circuit qubits and E_c represents the set of two-qubit gates between two vertices. We assume that |V_c | is less than or equal to |V_s |, the number of qubits in the system. Each edge (i, j) ∈ E_c has an associated weight w(i, j) denoting the frequency of that gate in the circuit.

Given a circuit $c\in \mathcal{C}$ with a graph representation G_c = (V_c , E_c , w) and a system graph G_s = (V_s , E_s , ), we map the circuit qubits to system qubits to minimize the infidelity $\mathcal{E}$ of that circuit. We search for a bijective map π: V_c → V_s which maps the circuit vertices to system vertices. This also gives a map between the edges in E_c and E_s , namely if e = (i, j) ∈ E_c , the corresponding map in the system graph is π(e) = (π(i), π(j)) ∈ E_s . For convenience, we use π(E_c ) = E_s and π(G_c ) = G_s to denote the mapping between the edge-sets and the graphs respectively. The minimum infidelity for this circuit is given by

$$\begin{equation}\mathcal{E}\left({G}_{c},{G}_{s}\right)={\mathrm{min}}_{\pi }\sum\limits _{e\in {E}_{c}}{\epsilon}\left(\pi \left(e\right)\right)\cdot w\left(e\right).\end{equation} \tag{ 1 }$$

The minimum average infidelity for a circuit batch $\mathcal{C}$ is given by

$$\begin{equation}\bar{\mathcal{E}}\left({G}_{s}\right)=\frac{1}{\vert \mathcal{C}\vert }\sum\limits _{c\in \mathcal{C}}\mathcal{E}\left({G}_{c},{G}_{s}\right).\end{equation} \tag{ 2 }$$

Let _S denote the infidelity function in which the gates in S are calibrated. Optimizing the calibration graph amounts to finding an optimal set S such that equation (2) is minimized. The naive solution would be to calibrate all the gates. However, in practice this is challenging, as the number of gates grows quadratically in the number of qubits and the calibration quality can degrade as the entire calibration sequence takes longer, especially for the gates calibrated in the beginning of the sequence. Thus, we assume we can only calibrate a certain number of gates |S| ⩽ Γ, where Γ represents a calibration budget. Taking the budget constraint into account, we have the minimal achievable average infidelity ${\bar{\mathcal{E}}}^{{\ast}}$, defined according to

$$\begin{equation}{\bar{\mathcal{E}}}^{{\ast}}={\mathrm{min}}_{\begin{subarray}{c}S\subseteq {E}_{s}\\ \vert S\vert {\leqslant}{\Gamma}\end{subarray}}\enspace \frac{1}{\vert \mathcal{C}\vert }\left[\sum\limits _{c\in \mathcal{C}}\mathcal{E}\left({G}_{c},{G}_{s}=\left({V}_{s},{E}_{s},{{\epsilon}}_{S}\right)\right)\right].\end{equation} \tag{ 3 }$$

Formally speaking, solving for equation (3) exactly is computationally hard, since the underlying problem in (1) is already NP-hard, i.e., a quadratic assignment problem [13]. Thus we resort to carefully constructed heuristic methods and aim to solve it approximately. To facilitate the necessary discussion, we introduce below a series of useful notations in the context of solving for an approximate solution of equation (3). We will extensively use them in the following section where we detail the heuristic methods.

To start, we consider a simple picture where we designate ₊ as the infidelity of a calibrated two-qubit gate and ₋ as the infidelity of a non-calibrated two-qubit gate. This assumption is not necessary but is pedagogically helpful for a clear and concise discussion of the notations we introduce next. For ₊ < ₋, we can simplify (1) as

$$\begin{equation}\mathcal{E}\left({G}_{c},{G}_{s}\right)={\mathrm{min}}_{\pi }\left[{{\epsilon}}_{+}\sum\limits _{\begin{subarray}{c}e\in {E}_{c}\\ \pi \left(e\right)\in S\end{subarray}}w\left(e\right)+{{\epsilon}}_{-}\sum\limits _{\begin{subarray}{c}e\in {E}_{c}\\ \pi \left(e\right)\notin S\end{subarray}}w\left(e\right)\right].\end{equation} \tag{ 4 }$$

This means that the problem of optimally mapping a circuit qubit to a physical qubit with the calibration set S reduces to the maximization of the first sum in (4). Provided that the calibration budget Γ is fixed, we may then succinctly write our problem as

$$\begin{equation}{W}_{{\Gamma}}={\mathrm{max}}_{\begin{subarray}{c}S\subseteq {E}_{s}\\ \vert S\vert {\leqslant}{\Gamma}\end{subarray}}\sum\limits _{c\in \mathcal{C}}\left[{\mathrm{max}}_{{\pi }_{c}}\sum\limits _{\begin{subarray}{c}e\in {E}_{c}\\ {\pi }_{c}\left(e\right)\in S\end{subarray}}w\left(e\right)\right],\end{equation} \tag{ 5 }$$

where W_Γ denotes the maximal achievable number of occurrences of two-qubit gates that can be mapped to calibrated gates in S with size Γ and π_c denotes the appropriate mapping per circuit c.

We first introduce maximum common edge subgraph (MCEs). The reason we are interested in MCEs is because, intuitively, the calibration set S we are after, in its graph representation, is to have a maximal overlap with a batch of input circuits in a typical scenario where the input circuit graphs presumably have more edges than the calibration budget. The MCEs between two non-weighted graphs consists of a maximum set of common edges. See below for the concrete definition.

Definition 3.1. (Maximum common edge subgraph (MCEs)). MCEs ∩(G₁, G₂, ..., G_n ) of a set of graphs G₁, G2, ..., G_n is the isomorphic subgraph with the largest number of edges.

For a sequence of graphs {G₁, G₂, ..., G_N }, the MCEs determined by sequentially calculating the pairwise MCEs, i.e., (((G₁ ∩ G₂) ∩ G₃) ... ∩ G_N ), is not the same as the MCEs of the graph sequence as defined in definition 3.1. The brute force method of finding MCEs of n graphs requires maximizing over permutations of vertex-mapping for all graphs. This scales exponentially in n. Therefore, we construct a MCEs of n graphs by composing pairwise MCEs operations, reducing the complexity to be linear in n instead. Note, however, that the process of pairwise MCEs determination is not associative (e.g. see figure 1). Since considering all N! orderings, where N is the total number of graphs that we aim to identify the MCEs of, is prohibitively expensive, we employ heuristics to determine candidate orderings, as we detail in the next section.

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Note that, thus far, the subgraph discussion above dealt with non-weighted graphs. Our problem, on the other hand, concerns weighted graphs where the edge weights of the input circuit graphs encode the number of occurrences of two-qubit gates. Thus, in the following, we modify the picture to accommodate weighted input graphs.

We start by introducing the notion of heaviest cumulative subgraph (HCs). This is defined as follows.

Definition 3.2. (Heaviest cumulative subgraph (HCs)). HCs is a common subgraph of multiple graphs, ∧(G₁, G₂, ..., G_n ), with a maximum total weight of edges found as:

$$\begin{equation}{W}_{\wedge }\left({G}_{1},{G}_{2},\dots ,{G}_{n}\right)={\mathrm{max}}_{{\pi }_{1},{\pi }_{2},\dots {\pi }_{n}}\sum\limits _{\begin{subarray}{c}e\in {\pi }_{1}\left({G}_{1}\right)\\ \cap {\pi }_{2}\left({G}_{2}\right)\\ \dots \\ \cap {\pi }_{n}\left({G}_{n}\right)\end{subarray}}\left[{w}_{{G}_{1}}\left({\tilde {e}}_{1}\right)+{w}_{{G}_{2}}\left({\tilde {e}}_{2}\right)+\cdots +{w}_{{G}_{n}}\left({\tilde {e}}_{n}\right)\right]\end{equation} \tag{ 6 }$$

where ${\tilde {e}}_{i}={\pi }_{i}^{-1}\left(e\right)$.

The HCs definition is closely related to our goal. To see this, recall that we aim to find mappings of the vertices of circuit graphs such that we maximize the number of two-qubit gates, encoded as the edge weights of the circuit graphs, that can be implemented using calibrated gates. As a concrete, pedagogical example, consider the HCs between two graphs G, a complete graph with two vertices, and H, a complete graph with three vertices. Let each edge of H have a different weight. Assume Γ = 1. The optimal calibration set S is then the HCs between graphs G and H, i.e., the mapping of G to H such that the cumulative edge weights is maximized.

In a non-trivial example, however, the HCs definition is insufficient to fully specify our problem. It is thus instructive to introduce the notion of MCCS here. To achieve our goal to minimize the average infidelity in equation (2), one can attempt to find circuit mappings such that the supergraph of the mapped circuits maximizes the sum of weights of the heaviest Γ edges. By construction, this supergraph will contain a subgraph with Γ edges that admits a large overlap with all the mapped input graphs. We refer to the supergraph as MCCS, whose definition we state below. In the special case of the binary gate fidelity model with _±, the problem of finding the best calibration graph (5) reduces to the problem of finding MCCS for a batch of input circuit graphs.

Definition 3.3. (Most compact cumulative supergraph (MCCS)). MCCS with respect to calibration budget Γ is the supergraph of a set of graphs, ∨_Γ(G₁, G₂, ..., G_n ), with the largest sum of weights on Γ edges. It can be found by maximizing the total weight of Γ heaviest edges as

$$\begin{equation}{W}_{{\Gamma}}\left({G}_{1},{G}_{2},\dots ,{G}_{n}\right)={\mathrm{max}}_{{\pi }_{1},{\pi }_{2},\dots {\pi }_{n}}\underset{\begin{subarray}{c}e\in {\pi }_{1}\left({G}_{1}\right)\\ \cup {\pi }_{2}\left({G}_{2}\right)\\ \dots \\ \cup {\pi }_{n}\left({G}_{n}\right)\end{subarray}}{\overset{{\Gamma}}{{\sum }^{\prime }}}\left[{w}_{{G}_{1}}\left({~{e}}_{1}\right)+{w}_{{G}_{2}}\left({~{e}}_{2}\right)+\cdots +{w}_{{G}_{n}}\left({~{e}}_{n}\right)\right],\end{equation} \tag{ 7 }$$

where the primed sum is for the first Γ largest elements.

So far, we have discussed a typical case of circuit graphs having more edges than the calibration budget Γ. In an atypical case where the input circuit graphs contain fewer edges than the budget, we can follow an alternative strategy, where we try to find a smallest sized supergraph that contains all of the input circuits as its subgraphs. Should the supergraph have the number of edges smaller or equal to Γ, one can simply calibrate all of the edges in the supergraph that is within the budget and obtain high fidelity. In this scenario, we do not need to consider the edge weights. To this end, we use the notion of a minimum common edge supergraph (mCES), whose definition appears below.

Definition 3.4. (Minimum common edge supergraph (mCES)). mCES identifies the smallest graph that contains all graphs from a set, ∪(G₁, G₂, ..., G_n ).

Having defined the necessary notations, in this section, we present two heuristic approaches that can minimize the calibration resource requirement: an approximate MCCS-finding algorithm (section 4.1) and a genetic algorithm (section 4.2). For pedagogical purposes, we first introduce in section 4.1.1 the MCCS algorithm at a high level using a flow diagram. Then we discuss the core part of the algorithm, i.e., a heuristic method to construct an optimal mapping of vertices from one graph to another in section 4.1.2. We further discuss speeding the method up using a beam search in section 4.1.3. Note we rely on all these techniques in the genetic algorithm shown in section 4.2.

4.1. Approximate MCCS-finding algorithm

4.1.1. General outline of the algorithm

Figure 2 shows the flow chart of our approximate MCCS algorithm. Briefly, we walk through the algorithm.

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We first receive a batch of quantum circuits. We then form a set of circuit graphs, taking graph isomorphism into account, i.e., the set contains elements that are not isomorphic to one another. In the case of weighted graphs, we use a modified definition of graph isomorphism, where we consider two weighted graphs G = (V₁, E₁, w₁) and H = (V₂, E₂, w₂) to be isomorphic if there is a bijective mapping π between the sets of vertices of the two graphs, π: V₁ → V₂, such that the mapping preserves weighted adjacency, i.e., w₁(e) = w₂(π(e)) ∀ e ∈ E₁. We also separately store a dictionary that contains the number of occurrences of each element, to be used later.

According to the flow chart (figure 2), there are two supergraph problems that need to be solved. In the case where the number of edges of the mCES between all of the elements of the set is less than Γ, the solution does not require using the number of occurrences of each element in the set of circuit graphs. Otherwise, we need to construct an MCCS, taking into account the number of occurrences.

To approximately find the MCCS, hereafter referred to as M, we order the graphs from largest to smallest by the number of edges. Ordering the graphs differently may affect the result as well as the execution time, but in our experience we did not observe any significant deviation varying the order for the sets of circuits studied here.

We now iterate over the elements in the order determined. With M initialized to a null graph for the first iteration, we find a qubit mapping π for the first graph element G in the ordered list, determined according to the steps detailed in section 4.1.2, which takes G and M as the input. The mapping aims to maximize the overlap between G and M. Once we have the mapped G, we merge it with M, where a merge here means that M = (V_M , E_M , w_M ) ↦ M = (V_M ∪ V_π(G), E_M ∪ E_π(G), w_M + w_π(G)). This process is repeated for the subsequent elements in the list, until all graphs from the list are considered. The resulting graph M is a cumulative supergraph of all graphs in the list. The final approximate solution for MCCS M_Γ can then be found by selecting Γ heaviest edges of M. See appendix B for further details.

Once the solution M_Γ is identified, we make a round of optimal mapping for each input circuit to M_Γ to maximize the overlap between M_Γ and each input circuit. This step is performed since the mappings used previously in constructing M are suboptimal for our maximal overlap problem with M_Γ. Our method uses the mappings identified at this step as the final mappings for each input circuit graph.

4.1.2. Algorithms for the optimal mapping

In this section, we show an algorithm that, given two graphs G and M, finds a mapping π of G such that π(G) and M have a maximal overlap. This may be considered an extension of the MCEs problem to weighted graphs. The algorithm for finding the most optimal mapping is a backtracking algorithm, which is similar to the depth-first search (DFS), except it does not go down all the possible branches but backtracks earlier based on a predictor function that checks whether the started mapping is worth completing based on the optimization goals. As a basis for this algorithm, we use the SplitP↓ [17, 23] algorithm with a modified predictor function (see appendix A for details). Instead of maximizing the number of edges of the common subgraph, we maximize the cumulative weight on the common subgraph to achieve a HCs. An additional criterion is used when there are multiple potential maps. In this scenario, we choose the map that incurs the least subgraph transformation cost (sTC) between π(G) and M, defined below. This criterion helps us minimize the number of heaviest edges in the final cumulative supergraph M.

Definition 4.1. (Subgraph transformation cost (sTC)). sTC S(G, H) between two weighted graphs G and H is the transformation cost (see below) on the graph formed by the set of their common edges

$$\begin{equation}S\left(G,H\right)=\sum\limits _{\begin{subarray}{c}e\in G\\ e\in H\end{subarray}}\vert {w}_{G}\left(e\right)-{w}_{H}\left(e\right)\vert .\end{equation} \tag{ 8 }$$

Definition 4.2. (Transformation cost (TC)). TC T(G, H) between two weighted graphs G and H includes the sum of weights for added/removed edges and change in weight for the common edges, i.e.,

$$\begin{equation}T\left(G,H\right)=\sum\limits _{\begin{subarray}{c}e\in G\\ e\notin H\end{subarray}}{w}_{G}\left(e\right)+\sum\limits _{\begin{subarray}{c}e\notin G\\ e\in H\end{subarray}}{w}_{H}\left(e\right)+\sum\limits _{\begin{subarray}{c}e\in G\\ e\in H\end{subarray}}\vert {w}_{G}\left(e\right)-{w}_{H}\left(e\right)\vert =\sum\limits _{e\in G\cup H}{f}_{C}\left({w}_{G}\left(e\right),{w}_{H}\left(e\right)\right),\end{equation} \tag{ 9 }$$

where w_G (e) = 0 if e ∉ G. In general the cost function f_C (w_G (e), w_H (e)) can be an arbitrary distance function on w_G (e) and w_H (e). We choose to use the minimum transformation cost since, when applied to a non-weighted case, it reduces the mapping problem to the MCEs problem (min_π T(π(G), H) = |G| + |H| − 2|G ∩ H|, where |G| denotes the number of edges of G).

Specifically, our mapping algorithm that identifies an optimal mapping of vertices of G to M repeatedly calls a search function. The search function looks for a HCs between the G and M with a pre-specified number of edges. If found, the function also returns the vertex maps from G to M, used to induce the HCs. By iteratively reducing the aforementioned pre-specified number of edges, starting from the number of edges of the smaller of the two input graphs G and M, we can determine the largest possible HCs between G and M.

The implementation of the search function is technically involved and we leave their fullest description to appendix A. Briefly, given the two input graphs G and M and the pre-specified number of edges, the function builds up a mapping using a DFS, starting with the empty mapping, and pairing an edge heuristically chosen from G with an appropriate edge from M at each level of the search tree. The function backtracks if a search in one branch has a little chance to beat the best results found so far. The function also backtracks if the calculated bound (defined below) is less than the pre-specified number of edges. The bound here is calculated as the number of edges that were mapped already plus the maximal number of edges that could be mapped based on their adjacency with respect to the mapped ones.

4.1.3. Beam search

While the backtrack algorithm used herein can be considered to be a more advanced version of DFS, it still scales poorly with the size of the graphs. To make our approach more scalable, we can set a threshold on the predicted improvement while exploring a branch, when compared to the best found so far. Specifically, the stronger condition requires the projected cumulative weight of the potential subgraph to exceed the best found, plus the added threshold. Otherwise the potential map is dismissed from further consideration. We can further explore multiple branches simultaneously, while capping the number of potential maps or walkers on the search tree to n, i.e., keeping only n most promising ones. A heuristic function is used to quantify the promise.

For a large number of qubits, circuit graphs in the batch may have small HCs, which would lead to a quick explosion in the size of the merged graph M. This results in a rapid increase in the computational resource required for the optimal mapping search described in the previous section. We thus limit the size of M, keeping the number of edges of M to be below kΓ. We achieve this by choosing to keep kΓ heaviest edges, while discarding the rest of the edges, should a determined M at any stage has more than kΓ edges, where k > 1.

4.2. Genetic algorithm

In this section, we discuss an alternative approach to solving the calibration problem. Genetic algorithm is considered a good candidate to solve graph theoretic problems [4, 6, 10]. We investigate the possibility of using genetic algorithms for optimal calibration.

We describe the genetic algorithm in algorithm 1. The genetic optimization algorithm has, in its memory, a population of subgraphs. In each generation, a fraction of that population is selected to move on to the next generation based on their fitness. In addition, we also produce mutated copies of fittest members of a population. In a mutation, a graph undergoes a random change in its structure. We also randomly select pairs of parents from the current population and use them in a crossover function to produce children for next generation. These children are expected to combine and improve the good feature of the parents. A small fraction is selected to mutate in which the graph goes a random change in its structure. The population size from generation to generation is held to a constant number. After a certain number of generations, the best member of the surviving population is returned as the optimal solution.

Algorithm 1. Outline of genetic algorithm.

Since we would like to find optimal calibration graphs that minimize the infidelity from equation (2), we take the negative of equation (2) as our fitness function. To calculate this fitness of a candidate calibration graph S, we minimize the average circuit infidelity (2) by finding the optimal vertex-map for each circuit in the circuit batch. We make a crucial note that calculating these fitnesses is already a challenging task because it requires us to calculate an optimal mapping from a circuit graph to a calibration graph. To calculate these optimal mappings, we use backtrack HCs and MCEs algorithms introduced earlier in section 4.1.2. The performance of our genetic algorithm is, therefore, closely tied to the performance of the function to calculate optimal mapping.

To mutate a graph G = (V, E) (with |E| = Γ) with a mutation rate p_m , we create another $\tilde {E},\vert \tilde {E}\vert ={\Gamma}$ where (1 − p_m )|E| edges are sampled from the original E and the remaining p_m |E| is sampled randomly from all possible edges from the vertex set V. To cross over two parents G₁ = (V, E₁) and G₂ = (V, E₂), we create two more graphs G₃ = (V, E₃) and G₄ = (V, E₄) where the edges E₃ and E₄ are produced by sampling from E₁ ∪ E₂ with the constraint |E₃| = |E₄| = Γ.

Here we show the results of optimization algorithms described earlier for three sets of graphs. The advantage of using the optimal calibration graph is demonstrated for a set of non-weighted and a set of weighted input circuit graphs, constructed from real-world quantum-computational jobs that were executed on an 11-qubit TIQC hosted at IonQ. A synthesized set of graphs, carefully selected to mimic realistic situations for systems with 10 to 20 qubits, is further used to benchmark the performance of our methods, demonstrating their scalability.

To demonstrate the quality of our methods, we compare them against the following four primitive mapping techniques. A completely unoptimized, trivial approach is to calibrate Γ random gates, then executing the circuits without any qubit mapping. Hereafter, this is referred to as the random method. A slightly optimized, but still a naive approach would be to count the number of gates in each circuit and calibrate Γ most frequently used ones, without consideration for qubit mapping. Hereafter, this is referred to as the naive approach. Recall, now, that, in our MCCS method, we used the final round of (re)mapping to determine the final mappings for each circuit graph to a determined system graph G_s , formed with the identified calibration set S. For the two primitive approaches, we can choose to turn this circuit (re)mapping on. The asterisk approaches are then the random or naive approaches with this (re)mapping step turned on. Note that these asterisked methods rely on our MCEs or HCs mapping functions.

We now estimate the fidelities for 30 most frequent non-weighted and 40 most frequent weighted graphs that occur in an actual quantum computer (see appendices C.1 and C.2 for details). Calibration graphs are generated for both batches using the MCCS algorithm, the genetic algorithm, and the four primitive techniques described previously. Average fidelities for all methods are estimated assuming that Γ calibrated gates have infidelity ₊ = 1%, while the rest has infidelities ₋ = 10%.

Figure 3(A) shows the average fidelity of the input quantum circuits as a function of the number of calibrated gates Γ for the non-weighted case. Upon inspection, we notice that all four methods that take advantage of our mapping function consistently perform better than the random method without mapping. For our particular example circuit batch, the MCCS algorithm shows the best fidelities for small Γ as well as for large ones, beating even the best random results with mapping, with the sample size of 100. Note the genetic algorithm also beats the best random for large Γ.

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Our methods can lead to an increasingly large level of savings as we dial up the fidelity requirement and Γ. Indeed, when employing our algorithms, up to about 13 quantum gates may be skipped from a calibration process to still result in the same fidelity over the naive calibration method (see figure 3(B)), and up to about 40 (not shown) compared to the average random calibration.

Figures 4(A) and (B) show the weighted counterparts to figures 3(A) and (B). We once again observe a large advantage over the random method for the entire range of Γ. We also observe that our MCCS, genetic, and best random* methods obtain better results than the naive* method for average fidelity larger than 85% or so, which corresponds to Γ > 7. The reduction in the Γ requirement compared to the naive method is large, up to 20 gate calibrations. The advantage of using our methods is clear, consistently requiring a smaller Γ to obtain a similar TIQC performance.

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We now benchmark the scalability of our algorithms with artificially generated batches of circuits for different system sizes. Each batch consists of five line-shaped graphs, five star-shaped graphs, five random trees, and N randomly selected small-diameter regular graphs, where N is the number of qubits. This particular composition was motivated by the line, star, and tree shapes appearing frequently in our real-world examples. See appendix C.3 for N = 12 examples and reference [16] for all of the benchmark circuits in their netlist representation. Small diameter, regular graphs of the form (k, d, n), where k is degree of the graph, d is the diameter of the graph, and n is the number of vertices, were selected as they are tailor made to leverage the all-to-all qubit connectivity available on a TIQC [20].

We compute the MCCS solutions for batches generated for six different system sizes, N = 10.. 20 qubits, and we consider Γ = N, 2N, 3N as an example. The number of calls to the search function, as a measure of the execution time, is shown in figure 5(A). We further estimate the number of calls M expected for the best random approach to achieve the same fidelity as our MCCS method, by first computing the best average fidelity obtained as a function of the number of random trials for the benchmark circuits, then extrapolating this to match the fidelity obtained by our MCCS method. We then convert this to the number of calls to the search function, which is of the form M/2 × (the number search calls for an MCCS solution), as per our method. We observe that for Γ = 2N solutions, the expected numbers of trials are M ≈ 700 for N = 10, M ≈ 800 for N = 12, and M ≈ 750 for N = 14 (see figure 5(A)), which results in more than 2.5 orders of magnitude higher in the number of search function calls compared to the MCCS method. Note the runtime can actually be much longer, as the upper bound on the 90% confidence interval spans several orders up due to the Poisson distribution of the probability to find the solution randomly.

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For each Γ = N, 2N, 3N cases we consider, we estimate the average fidelity expected from our benchmark batch of circuits using the gate infidelities _± used previously. We find that it takes more than twice the number of calibrated gates to reach the same average fidelities if the naive approach is used. The advantage in the Γ requirement grows with the system size according to the trends shown in figure 5(B). Note, to reach the same fidelity, the naive approach can demand as large as 80 additional calibrations, on top of 60 already required from the better-performing MCCS method, for the 20-qubit instance.

In this paper, we showed that for both non-weighted and weighted graphs, a judicious mapping between circuit qubits and system qubits can have a significant effect on the fidelity. In both cases, our mapping algorithm increased the average algorithm fidelity from about 70% for unmapped executions, to over 90%, in our hypothetical scenario where the calibrated gates have the fidelity of 99% and the non-calibrated gates have the fidelity of 90%. If we focus on the methods that leverage qubit mapping, calibrating the gate-sets determined in part by our backtrack algorithm gives a consistently better performance over the fidelity range of interest for both weighted and non-weighted graphs, when compared to those obtained by the naive method of calibrating simply the most frequently used gates. While the MCCS algorithm outperforms other approaches, the genetic algorithm can compete with it for a large calibration budget Γ > 15. We note that, aided by our (re)mapping algorithm, even a random calibration set can give a performance close to the one we obtain using backtracking or genetic algorithm. We demonstrate though that a random sampling method can take more than orders of magnitude longer than our backtracking algorithm to reach a target fidelity.

In using the genetic algorithm to find the optimal calibration graph, we notice that the genetic algorithm sometimes outperforms the MCCS algorithm in terms of the average fidelity for large Γ. The genetic algorithm, however, utilizing the same HCs and MCEs for its fitness function, consumes a lot of computational resources due to the stochastic evolution of an ensemble of candidate solutions. It would be interesting to investigate other neural-network based methods, such as deep-learning, which could facilitate a more efficient fusion with the backtrack algorithm [1], or a nested (multi-level) candidate search approach [18]. We leave this line of investigation as a future work.

In a scenario where quantum gates can reliably be calibrated fast and we know how the gates become uncalibrated over time, it is possible to expand the scope of our work to use it as a part of 'runtime' calibration process, beyond the initial calibration as was used in this paper. Further, our work can be integrated with a higher-level, optimizing compiler toolchain for quantum circuits, where the input circuits can be re-synthesized using replacement rules, templates, and/or swap insertions, in order to amplify similarities between the circuits included in a single batch. This will likely admit a better quality of quantum computational results. These exciting example avenues of research that are of direct relevance to our work form yet another set of lines of investigation that will be a part of our future work.

Our work also opens up a possibility to bootstrap further progress in quantum circuit compiling. There are quantum algorithms that hold promise in accelerating numerical optimization [9]. In the future, it may be possible to use a smaller quantum computer to optimize the calibration routine for a larger quantum computer. This is one instance of bootstrapping where quantum computers become progressively better.

While, in this work, we focus on ion-trap computers with all-to-all connectivity, an adaptation of the ideas we discuss could be useful for architectures with a more restrictive connectivity like superconducting qubits and for modularized topologies, where several strongly-connected modules communicate with a few channels. The graph theoretic technique we discuss above can be modified to reduce the routing and shuttling time in such systems with limited connectivity.

Should there be an emergent graph that is suitable for a large number of quantum programs, such a graph may inform and guide the quantum hardware designers to prioritize the development relevant technologies. A performance quantum compiler that then leverages what may become a standard architecture of a quantum computer could subsequently be developed to enable more user-friendly quantum application development environment.

With the massive potential lying ahead of us, we hope that our work helps a broad community of quantum computing and communications in pursuit of a scalable systems design. We are certain, in many challenges to come in quantum enterprise, our present and future works proposed herein will prove valuable.

All data that support the findings of this study are included within the article (and any supplementary files).

We base our implementation of the MCEs search on the SplitP↓ algorithm [17, 23], which is a k-down branch and bound algorithm. The pseudocode for the heaviest cumulative subgraph (HCs) search derived from it is shown in algorithm 2. We attempt to find HCs of a pre-specified number of edges, hereafter referred to as a goal, starting from the largest possible. At each step we also check the sum of edge weights of the found HCs. We terminate our algorithm when this sum no longer increases. This is done to cover the cases where a smaller subgraph can have a larger cumulative weight than a larger subgraph.

Algorithm 2. HCs backtrack k-down algorithm.

For each goal, we initialize an empty map, and pass all the edges from G and H as unlabeled, setting no restrictions on their mapping. The search function then iterates through different possibilities of this mapping at each level of the search tree, updating the labels based on the adjacency imposed by the map built so far. The function backtracks if a search in one branch has a little chance to beat the best results found so far. The function also backtracks if the calculated bound (defined below) is less than the goal. The bound here is calculated as the number of edges that were mapped already plus the maximal number of edges that could be mapped based on their adjacency with respect to the mapped ones.

Heuristics, used to determine which branches to follow first, aim to maximize the cumulative weight on the common subgraph as well as to minimize the sTC. The calculation is similar to the calculation of the bound described above. For each branch we estimate the maximum cumulative weight that can be found on the remaining edges taking into account their labeling. Similarly, we estimate the minimum possible sTC. The branches are then visited starting from the most promising ones. Following this ordering, we can then restrict the number of branches for the beam search by only visiting the first N, or by setting a threshold on the expected cumulative weight.

We provide a pseudocode (see algorithm 3) for the optimal calibration search algorithm based on the approximate most compact common supergraph (MCCS) and the minimum common edge supergraph (mCES). The main idea behind the suggested algorithm is a reduction of the MCCS and mCES to iterative pairwise HCs and MCEs, which can only be done approximately for more than two graphs.

Algorithm 3. Optimal calibration graph search based on MCCS and mCES

Just like the MCEs, the mCES finding operation is not associative. This means that, for a set of more than two graphs, the exact solution cannot be found by sequentially solving for the mCES for a pair of graphs as (((G₁ ∪ G₂) ∪ G₃) ... ∪ G_N ). The same issue takes place for MCCS and HCs. It becomes even more complicated if we want to optimize MCCS for a specific Γ. Instead of targeting a specific Γ, we minimize the number of heaviest edges in MCCS by minimizing sTC in HCs as described in the previous section.

Due to the non-associativity of both MCCS and mCES and the non-uniqueness of their solutions, the result of sequentially merging graphs in a list depends on the order of the list. Depending on the properties of the set of graphs, a particular ordering may result in a closer to the exact MCCS solution than others. One can consider different orderings based on certain parameters such as the number of occurrences of the isomorphic input graphs in the set, the graph edge weight distribution, the graph diameter, the maximum degree of each graph, etc. We decided to order the graphs in a descending order of the number of edges. Ordering by other criteria did not make any significant difference in the end result for the batches studied.

Since we find a general MCCS solution regardless of Γ, the optimal mapping of each graph after the MCCS is trimmed is now different. To correct for this, instead of using the maps found during MCCS, we find new maps for each graph.

C.1. Batch of non-weighted circuit graphs

23 244 non-trivial (more than one two-qubit gate) circuit graphs were extracted from the logs of a trapped-ion quantum computer hosted at IonQ. Once checked for graph-isomorphism, 484 unique non-weighted circuit graphs were sorted by the number of occurrences. The 30 most common graphs(see figure C1) are used as non-weighted input for the algorithms discussed in the main text (see section 5). Figure C2 shows the histogram of the number of occurrences of the different graphs (accounting for graph isomorphism) and the histogram of sizes (number of edges) of the graphs.

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C.2. Batch of weighted circuit graphs

39 958 non-trivial (more than one two-qubit gate) circuit graphs were extracted from the logs of a trapped-ion quantum computer hosted at IonQ. Once checked for graph-isomorphism, 300 unique non-weighted circuit graphs were sorted by the number of occurrences. The 40 most common graphs (see figure C3) are used as weighted input for the algorithms discussed in the main text (see section 5). Figure C4 shows the histogram of the number of occurrences of the different graphs (accounting for graph isomorphism) and the histogram of sizes (number of edges) of the graphs.

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C.3. Benchmark circuit graphs

To benchmark the scalability of our algorithms, we generated artificial batches of circuits for different system sizes. Each batch consists of five line-shaped graphs, five star-shaped graphs, five random trees, and N randomly selected small-diameter regular graphs, where N is the number of qubits. This particular composition was motivated by the line, star, and tree shapes appearing frequently in our real-world examples (see appendices C.1 and C.2). Small diameter, regular graphs of the form (k, d, n), where k is degree of the graph, d is the diameter of the graph, and n is the number of vertices, were selected as they are tailor made to leverage the all-to-all qubit connectivity available on a TIQC [20].

All benchmark circuit graphs used here are available on GitHub [16]. Circuit graphs from a benchmark batch generated for N = 12 are shown below as an example (see figure C5).

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