Elsevier

Microelectronics Journal

Volume 115, September 2021, 105205
Microelectronics Journal

Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications

https://doi.org/10.1016/j.mejo.2021.105205Get rights and content

Highlights

  • Design of high performance 20T Hybrid full adder (FA) is proposed.

  • Best performance at supply voltage (0.6–1.5V) and process corner.

  • Full voltage swing at all the internal and external nodes.

  • Proposed Hybrid FA reported low delay and power delay product (PDP) against reviewed circuits.

Abstract

Most of the full adder (FA) circuits are implemented through a hybrid logic style using three different modules. The principal peculiarity of these hybrid logic style-based FA cells is that each module could be optimized individually to improve the circuit performance. A high-performance 1-bit hybrid FA cell is proposed with pass transistor logic and transmission gate logic in the present work. The proposed FA circuit is implemented using 20-transistors to achieve optimum performance. The proposed circuit is simulated in Cadence virtuoso tool by using 90-nm process CMOS technology. Comparison of the design matrices for the proposed 1-bit hybrid FA cell against the five different reported FA circuits is also carried out. The present study reported 13.01–54.93 % and 13.01–59.20 % improvement in terms of delay and power delay product (PDP), respectively, compared to other FA designs. The proposed circuit is also investigated in different supply voltages (0.6–1.5V). Furthermore, the FA circuit is verified in different process corner conditions to check the robustness.

Introduction

High performance is one of the essential features in electronic devices, like personal digital assistants (PDAs), cellular phones, and Internet of Things (IoT) devices [1]. High-speed circuits are needed for high performance to cope with the high operating frequency and complex designs. In the application-specific electronic devices, digital signal processors or microprocessors have Arithmetic and Logic Unit (ALU) as a primary block. The adder module is the core element of the ALU circuit. FA is also the fundamental building block for several arithmetic circuit operations, for example, multipliers, compressors, and comparators. Hence, improvement in the performance of the adder circuits is one of the leading research areas of the VLSI researchers to enhance the performance of the digital system. Different static logic styles are used, and these logic styles are generally divided into two groups: conventional logic and hybrid logic styles [[2], [3], [4], [5], [6]].

In the conventional style-based full adder, only one logic is used to implement the whole FA design. The complementary metal-oxide-semiconductor (CMOS) based FA is an example of the classical approach, which is implemented using pull-up (PMOS) and pull-down (NMOS) network. In this approach, 28-transistors are used to realize the full adder. This circuit offers full voltage swing at all the external and internal nodes and provides robustness against the transistor sizing and voltage scaling. However, the major drawback of this FA design is the presence of PMOS block, and due to the low mobility of PMOS, performance is degraded; therefore, to improve the performance, PMOS transistors are sized up [2].

Another classical approach to implement the FA design is the complementary pass-transistor logic style (CPL). This CPL logic style uses a dual rail structure with 32-transistors to implement the FA design. This structure offers a full voltage swing at the output node, high speed, and good driving capabilities. However, the main demerit of this circuit is high power dissipation owing to a large number of internal nodes in the cell. Another problem with this FA design is that the layout is complex because of the irregular transistor arrangement [3].

Pass transistor logic (PTL) is also a classical approach that can be used to realize the FA design. However, the threshold loss problem arises when logic "1" and logic "0" pass-through NMOS and PMOS transistors, respectively. Therefore, to resolve the issue of the threshold problem, a new logic style is used, which is the transmission gate (TG) logic style. To implement the FA using the TG logic style, 20-transistors are used. This type of adder has low power consumption; however, the main demerit of this type of adder is the weak driving capability [2,3].

Subsequently, FA is realized using a hybrid style to overcome the problem of conventional style-based FA circuits. In the hybrid style, multiple classical styles optimize the circuit's performance [5,6].

In a hybrid FA structure, three different modules are used. In the first module, the two input signals (A& B) are applied that deliver full swing signals (XOR & XNOR) at the output. These XOR-XNOR signals should have good driving proficiency to drive the SUM and CARRY circuits. The second and third modules generate the sum and carry output correspondingly using the outputs of the first module and the third carry input signal (CIN). This type of FA design offers the full voltage swing at the output node and good driving capability to transmit the signals further [[6], [7], [8], [9], [10]].

Furthermore, hybrid FA is classified based on its internal structures. Aguirre [9] presented the internal logic architecture of the FA, which is shown in Fig. 1 (a). This first module (XOR/XNOR) of FA is realized using double pass transistor logic (DPL). Module second and module third are implemented using XOR/XNOR and AND/OR gate, respectively. Another internal configuration of the FA proposed by Kumar [12] is presented in Fig. 1(b). The first module (XOR/XNOR) of this FA configuration is realized through swing restored complementary pass transistor logic (SR-CPL). The second and third modules are implemented using XOR/XNOR and NAND/NOR gates, respectively. One more internal architecture of the hybrid FA design given by Valashani [13] is displayed in Fig. 1(c). In this design, the XOR- XNOR functions are produced through the first module, and these generated signals show good driving capability and provide the full output swing concurrently. The second and third modules are the SUM and CARRY circuits realized using the TG and MUX circuits.

The main advantage of these hybrid logic styles is that one can mend each module individually and improve performance through good interfacing among different modules. On the other hand, the performance of this type of hybrid logic is degraded if it is implemented through different cascading stages due to reducing in the driving capability.

A high-performance XOR-XNOR design is used in this paper, proposed by Kandpal et al., 2018 [14]. The Proposed XOR-XNOR is realized using CPL logic with one static inverter and has a symmetrical structure without cross-coupling. Further, XOR-XNOR provides simultaneous XOR-XNOR logic, balanced output, and exhibits full voltage swing in all internal and external nodes. The designed XOR-XNOR is used as the first module of the hybrid FA design. Module II and III are used to implement sum and carry logic in a FA and can be implemented using different topologies in CMOS. Therefore, the performance evaluation of the proposed XOR-XNOR module is to be checked in FA. In this paper, the XOR-XNOR design is used in the FA, which is used to resolve compabilities issues and improve the Full adder's performance. In the proposed FA design, module II and module III are implemented using the TG and multiplexer (MUX). It uses only 20-transistors and reported low power consumption with lesser delay. In the present study, the FA circuit is simulated using the Cadence Virtuoso tool in 90 nm CMOS technology at 1.2 VDD.

The rest of this work is organized as follows. Section II gives a brief introduction to the proposed XOR-XNOR circuits. The hybrid FA design with module II and Module III is discussed in section III. Section IV explains the simulation results and analytical comparisons, and Section V gives the conclusion.

Section snippets

XOR-XNOR design

There are primarily two methods for designing the XOR-XNOR circuit in the literature. The XOR function is generated at first in the foremost method, and then the XNOR function is produced by using an inverter [2,11,20]. XOR and XNOR signals are delivered separately, due to which false switching and glitches arise in the output of the second and third modules. In another method, XOR–XNOR signals are generated simultaneously at the output; therefore, the delay variation among XOR-XNOR signals

Proposed full adder design

The proposed FA circuit is realized as presented in Fig. 1(c) using three different modules. First, the second and third module generates the sum and carry output, respectively. Second, each module is implemented independently to optimized the circuit performance in terms of power consumption, delay, and area. These modules are discussed in the following section.

Comparative study of the proposed design

In this section, comparison results of different designs of XOR-XNOR and FA are discussed. The results are shown in the upcoming subsection for the performance metrics.

Conclusion

The present study mainly focuses on the circuit design level, choosing a proper logic style for implementing the FA circuit. A hybrid style gives liberty to VLSI designers to select different modules to implement the circuit as per their prerequisites. In the present work, a new design of a 1-bit FA is presented on the hybrid design scheme using the 20-transistors. The proposed method alleviates the threshold voltage problem and enhances the driving capability. A comprehensive comparison is

Author statement

Jyoti Kandpal: Conceptualization; Methodology; Investigation; Formal analysis; Writing – original draft. Abhishek Tomar: Conceptualization; Supervision; Validation; Writing – review & editing. Mayur Agarwal: Methodology; Supervision; Writing – review & editing.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this manuscript.

No conflict of interest exits in the submission of this manuscript.

Acknowledgment

This work is supported by a fellowship from the Ministry of Human Resource and Development, Government of India, through the Technical Education Quality Improvement Programme-III (TEQIP-III), India.

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