Abstract
The advancement of Silicon CMOS technology has led information technology innovation for decades. However, scaling transistors down according to Moore’s law is almost reaching its limitations. To improve system performance, cost, and energy efficiency, vertical-optimization in multiple layers of the computing stack is required. Technological awareness in terms of devices and circuits could enable informed system-level decisions. For example, graphene is a promising material for extremely scaled high-speed transistors because of its remarkably high mobility, but it can not be used in integrated circuits as a result of the high leakage current from its zero bandgap. In this article, we discuss the fundamental physics of transistors and their ramifications on system design to assist device-level technology consideration during system design. Additionally, various emerging devices and their utilization on a vertically-optimized computing stack are introduced. This article serves as a survey of emerging device technologies that may be relevant in these areas, with an emphasis on making the descriptions approachable by system and software designers to understand the potential solutions. A basic vocabulary will be built to understand how to digest technical content, followed by a survey of devices, and finally a discussion of the implications for future processing systems.
- Affan Abbasi, Robert Murphree, Sajib Roy, Marvin Suggs, John Fraley, H. Alan Mantooth, Jia Di, and Tobias Erlbacher. 2019. High-temperature memory design, implementation, and characterization in 1m SiC CMOS technology. In Proceedings of the Additional Conferences (Device Packaging, HiTEC, HiTEN, & CICMT), Vol. 2019. International Microelectronics Assembly and Packaging Society, 000011–000015.Google Scholar
- Shamim Ahmed, Arman Ur Rashid, Md Maksudul Hossain, Tom Vrotsos, A. Matthew Francis, and H. Alan Mantooth. 2019. DC modeling and geometry scaling of SiC low-voltage MOSFETs for integrated circuit design. IEEE J. Emerg. Select. Top. Power Electron. 7, 3 (2019), 1574–1583.Google ScholarCross Ref
- Mohamed M. Sabry Aly, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, Mehdi Asheghi, Jeff Bokor, Franz Franchetti et al. 2015. Energy-efficient abundant-data computing: The N3XT 1,000 x. Computer 48, 12 (2015), 24–33. Google ScholarDigital Library
- Aporva Amarnath, Javad Bagherzadeh, Jielun Tan, and Ronald G. Dreslinski. 2019. 3DTUBE: A design framework for high-variation carbon nanotube-based transistor technology. In Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’19). IEEE, 1–6.Google Scholar
- Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, and Ronald G. Dreslinski. 2017. A carbon nanotube transistor-based RISC-V processor using pass transistor logic. In Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’17). IEEE, 1–6.Google Scholar
- Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Jörg Henkel, and Yogesh Singh Chauhan. 2018. Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance. IEEE Access 6 (2018), 52754–52765.Google ScholarCross Ref
- Uygar E. Avci, Daniel H. Morris, and Ian A. Young. 2015. Tunnel field-effect transistors: Prospects and challenges. IEEE J. Electron Dev. Soc. 3, 3 (2015), 88–95.Google ScholarCross Ref
- Arieh Aviram and Mark A. Ratner. 1974. Molecular rectifiers. Chem. Phys. Lett. 29, 2 (1974), 277–283.Google ScholarCross Ref
- Phaedon Avouris, Zhihong Chen, and Vasili Perebeinos. 2010. Carbon-based electronics. In Nanosci. Technol.: Collect. Rev. Nature J. World Scientific, Singapore, 174–184.Google Scholar
- Ahmedullah Aziz, Evelyn T Breyer, An Chen, Xiaoming Chen, Suman Datta, Sumeet Kumar Gupta, Michael Hoffmann, Xiaobo Sharon Hu, Adrian Ionescu, Matthew Jerry et al. 2018. Computing with Ferroelectric FETs: Devices, Models, Systems, and Applications. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’18). IEEE, 1289–1298.Google ScholarCross Ref
- Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, and Ronald G. Dreslinski. 2020. R2D3: A reliability engine for 3D parallel systems. In Proceedings of the 57th Annual Design Automation Conference (DAC’20). Google ScholarDigital Library
- J. Bagherzadeh and V. Bertacco. 2017. 3DFAR: A three-dimensional fabric for reliable multi-core processors. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE’17). 310–313. Google ScholarDigital Library
- P. Batude, M. Vinet, B. Previtali, C. Tabone, C. Xu, J. Mazurier, O. Weber, F. Andrieu, L. Tosti, L. Brevard et al. 2011. Advances, challenges and opportunities in 3D CMOS sequential integration. In Proceedings of the International Electron Devices Meeting. IEEE, 7–3.Google Scholar
- Kerry Bernstein, Ralph K. Cavin, Wolfgang Porod, Alan Seabaugh, and Jeff Welser. 2010. Device and architecture outlook for beyond CMOS switches. Proc. IEEE 98, 12 (2010), 2169–2184.Google ScholarCross Ref
- Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Pat Morrow, Donald W. Nelson, Daniel Pantuso et al. 2006. Die stacking (3D) microarchitecture. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 469–479. Google ScholarDigital Library
- Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, and Giovanni de Micheli. 2014. System level benchmarking with yield-enhanced standard cell library for carbon nanotube VLSI circuits. ACM J. Emerg. Technol. Comput. Syst. 10, 4 (2014), 33. Google ScholarDigital Library
- Mark T. Bohr and Ian A. Young. 2017. CMOS scaling trends and beyond. IEEE Micro 37, 6 (2017), 20–29.Google ScholarCross Ref
- Mattias Borg, Heinz Schmid, Kirsten E Moselund, Davide Cutaia, and Heike Riel. 2015. Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si. J. Appl. Phys. 117, 14 (2015), 144303.Google ScholarCross Ref
- Gerald J. Brady, Austin J. Way, Nathaniel S. Safron, Harold T. Evensen, Padma Gopalan, and Michael S. Arnold. 2016. Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs. Sci. Adv. 2, 9 (2016), e1601240.Google ScholarCross Ref
- Geoffrey W. Burr, Matthew J. Breitwisch, Michele Franceschini, Davide Garetto, Kailash Gopalakrishnan, Bryan Jackson, Bülent Kurdi, Chung Lam, Luis A. Lastras, Alvaro Padilla et al. 2010. Phase change memory technology. J. Vac. Sci. Technol. B, Nanotechnol. Microelectron.: Mater., Process., Meas. Phenom. 28, 2 (2010), 223–262.Google ScholarCross Ref
- Ilkwon Byun, Dongmoon Min, Gyu-hyeon Lee, Seongmin Na, and Jangwoo Kim. 2020. CryoCore: A fast and dense processor architecture for cryogenic computing. In Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA’20). IEEE, 335–348. Google ScholarDigital Library
- Hernan A. Castro. 2016. Accessing memory cells in parallel in a cross-point array. U.S. Patent 9,312,005.Google Scholar
- Robert S. Chau. 2008. Emerging device nanotechnology for future high-speed and energy-efficient VLSI: Challenges and opportunities. In Proceedings of the 38th European Solid-State Device Research Conference (ESSDERC’08). IEEE, 1–3.Google Scholar
- An Chen. 2016. A review of emerging non-volatile memory (NVM) technologies and applications. Solid-State Electron. 125 (2016), 25–38.Google ScholarCross Ref
- Lin Chen, Fuxi Cai, Ugo Otuonye, and Wei D. Lu. 2015. Vertical Ge/Si core/shell nanowire junctionless transistor. Nano Lett. 16, 1 (2015), 420–426.Google ScholarCross Ref
- Xiaoming Chen, Xiaoyu Sun, Panni Wang, Suman Datta, Xiaobo Sharon Hu, Xunzhao Yin, Matthew Jerry, Shimeng Yu, Ann Franchesca Laguna, Kai Ni et al. 2019. The impact of ferroelectric FETs on digital and analog circuits and architectures. IEEE Design Test 37, 1 (2019), 79–99.Google ScholarCross Ref
- Yang Yin Chen, Robin Degraeve, Bogdan Govoreanu, Sergiu Clima, Ludovic Goux, Andrea Fantini, Gouri Sankar Kar, Dirk J Wouters, Guido Groeseneken, and Malgorzata Jurczak. 2013. Postcycling LRS retention analysis in HfO 2/Hf RRAM 1T1R device. IEEE Electron. Device Lett. 34, 5 (2013), 626–628.Google ScholarCross Ref
- Zhihong Chen, Yu-Ming Lin, Michael J. Rooks, and Phaedon Avouris. 2007. Graphene nano-ribbon electronics. Phys. E: Low-dimension. Syst. Nanostruct. 40, 2 (2007), 228–232.Google ScholarCross Ref
- Rui Cheng, Shan Jiang, Yu Chen, Yuan Liu, Nathan Weiss, Hung-Chieh Cheng, Hao Wu, Yu Huang, and Xiangfeng Duan. 2014. Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics. Nature Commun. 5 (2014), 5143.Google ScholarCross Ref
- Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory. In ACM SIGARCH Computer Architecture News, Vol. 44. IEEE Press, 27–39. Google ScholarDigital Library
- Woo Young Choi, Byung-Gook Park, Jong Duk Lee, and Tsu-Jae King Liu. 2007. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron. Device Lett. 28, 8 (2007), 743–745.Google ScholarCross Ref
- Youngdon Choi, Ickhyun Song, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Duckmin Kwon, Jung Sunwoo et al. 2012. A 20nm 1.8 V 8Gb PRAM with 40MB/s program bandwidth. In Proceedings of the IEEE International Solid-State Circuits Conference. IEEE, 46–48.Google Scholar
- David T. Clark, Ewan P. Ramsay, A. E. Murphy, Dave A. Smith, Robin Thompson, R. A. R. Young, Jennifer D. Cormack, C. Zhu, S. Finney, John Fletcher et al. 2011. High-temperature silicon carbide CMOS integrated circuits. In Materials Science Forum, Vol. 679. Trans Tech Publications, 726–729.Google ScholarCross Ref
- Jean Pierre Colinge. 2007. Multi-gate soi mosfets. Microelectron. Eng. 84, 9-10 (2007), 2071–2076. Google ScholarDigital Library
- Jean-Pierre Colinge. 2012. Junctionless transistors. In Proceedings of the IEEE International Meeting for Future of Electron Devices. IEEE, 1–2.Google ScholarCross Ref
- Ian Cutress. 2018. The Intel 9th Gen Review: Core i9-9900K, Core i7-9700K and Core i5-9600K Tested. Retrieved November 3, 2019 from https://www.anandtech.com/show/13400/intel-9th-gen-core-i9-9900k-i7-9700k-i5-9600k-review.Google Scholar
- L. Czornomaz, N. Daix, P. Kerber, K. Lister, Daniele Caimi, C. Rossel, Marilyne Sousa, E. Uccelli, and Jean Fompeyrine. 2013. Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon. In Proceedings of the European Solid-State Device Research Conference (ESSDERC’13). IEEE, 143–146.Google ScholarCross Ref
- L. Czornomaz, V. Djara, V. Deshpande, E. O’Connor, M. Sousa, D. Caimi, K. Cheng, and J. Fompeyrine. 2016. First demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si using selective epitaxy and standard FEOL processes. In Proceedings of the IEEE Symposium on VLSI Technology. IEEE, 1–2.Google Scholar
- L. Czornomaz, E. Uccelli, M. Sousa, V. Deshpande, V. Djara, D. Caimi, M. D. Rossell, R. Erni, and J. Fompeyrine. 2015. Confined epitaxial lateral overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates. In Proceedings of the Symposium on VLSI Technology (VLSITechnology’15). IEEE, T172–T173.Google Scholar
- N. Daix, E. Uccelli, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa, H. Siegwart, C. Marchiori, J. M. Hartmann, K.-T. Shiu et al. 2014. Towards large size substrates for III–V co-integration made by direct wafer bonding on Si. APL Mater. 2, 8 (2014), 086104.Google ScholarCross Ref
- Robert H. Dennard, Fritz H. Gaensslen, V. Leo Rideout, Ernest Bassous, and Andre R. LeBlanc. 1974. Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circ. 9, 5 (1974), 256–268.Google ScholarCross Ref
- Sujay B. Desai, Surabhi R. Madhvapathy, Angada B. Sachid, Juan Pablo Llinas, Qingxiao Wang, Geun Ho Ahn, Gregory Pitner, Moon J. Kim, Jeffrey Bokor, Chenming Hu et al. 2016. MoS2 transistors with 1-nanometer gate lengths. Science 354, 6308 (2016), 99–102.Google ScholarCross Ref
- V. Deshpande, V. Djara, E. O’Connor, P. Hashemi, K. Balakrishnan, M. Sousa, D. Caimi, A. Olziersky, L. Czornomaz, and J. Fompeyrine. 2015. Advanced 3D monolithic hybrid CMOS with sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI fin pFETs. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’15). IEEE, 8–8.Google Scholar
- Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester, and Trevor Mudge. 2010. Near-threshold computing: Reclaiming Moore’s law through energy efficient integrated circuits. Proc. IEEE 98, 2 (2010), 253–266.Google ScholarCross Ref
- S. Dünkel, Martin Trentzsch, Regina Richter, Patrick Moll, Christine Fuchs, Oliver Gehring, Mateusz Majer, Stefan Wittek, B. Müller, Thomas Melde et al. 2017. A FeFET-based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’17). IEEE, 19–7.Google ScholarCross Ref
- T. Dürkop, S. A. Getty, Enrique Cobas, and M. S. Fuhrer. 2004. Extraordinary mobility in semiconducting carbon nanotubes. Nano Lett. 4, 1 (2004), 35–39.Google ScholarCross Ref
- Marie D’angelo and Iwao Matsuda. 2019. Basics and families of monatomic layers: Single-layer 2D materials. In Monatomic Two-Dimensional Layers. Elsevier, 3–22.Google Scholar
- Semiconductor Engineering. [n.d.]. Multiple patterning. Retrieved from https://semiengineering.com/knowledge_centers/manufacturing/patterning/multipatterning/.Google Scholar
- Hadi Esmaeilzadeh, Emily Blem, Renee St. Amant, Karthikeyan Sankaralingam, and Doug Burger. 2011. Dark silicon and the end of multicore scaling. In Proceedings of the 38th Annual International Symposium on Computer Architecture (ISCA’11). IEEE, 365–376. Google ScholarDigital Library
- Richard Fackenthal, Makoto Kitagawa, Wataru Otsuka, Kirk Prall, Duane Mills, Keiichi Tsutsui, Jahanshir Javanifard, Kerry Tedrow, Tomohito Tsushima, Yoshiyuki Shibahara et al. 2014. 19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC’14). IEEE, 338–339.Google ScholarCross Ref
- Aaron D. Franklin, Mathieu Luisier, Shu-Jen Han, George Tulevski, Chris M. Breslin, Lynne Gignac, Mark S. Lundstrom, and Wilfried Haensch. 2012. Sub-10 nm carbon nanotube transistor. Nano Lett. 12, 2 (2012), 758–762.Google ScholarCross Ref
- John Gantz and David Reinsel. 2012. The digital universe in 2020: Big data, bigger digital shadows, and biggest growth in the far east. IDC iView: IDC Anal. Future 2007, 2012 (2012), 1–16.Google Scholar
- Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Nasser Masoumi, and Deming Chen. 2015. Analytical SPICE-compatible model of Schottky barrier-type GNRFETs with performance analysis. IEEE Trans. Very Large Scale Integr. Syst. 24, 2 (2015), 650–663.Google ScholarDigital Library
- Bhargava Gopireddy, Dimitrios Skarlatos, Wenjuan Zhu, and Josep Torrellas. 2018. HetCore: TFET-CMOS hetero-device architecture for CPUs and GPUs. In Proceedings of the ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA’18). IEEE, 802–815. Google ScholarDigital Library
- Omid Habibpour, Zhongxia Simon He, Wlodek Strupinski, Niklas Rorsman, and Herbert Zirath. 2017. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication. Sci. Rep. 7 (2017), 41828.Google Scholar
- Linden Harrison. 2006. An introduction to Depletion-mode MOSFETs. Retrieved from https://www.mikrocontroller.net/attachment/389314/IntroDepletionModeMOSFET.pdf.Google Scholar
- John L. Hennessy and David A. Patterson. 2011. Computer Architecture: A Quantitative Approach. Elsevier. Google ScholarDigital Library
- John L. Hennessy and David A. Patterson. 2019. A new golden age for computer architecture. Commun. ACM 62, 2 (2019), 48–60. Google ScholarDigital Library
- Gage Hills, Christian Lau, Andrew Wright, Samuel Fuller, Mindy D. Bishop, Tathagata Srimani, Pritpal Kanhaiya, Rebecca Ho, Aya Amer, Yosi Stein et al. 2019. Modern microprocessor built from complementary carbon nanotube transistors. Nature 572, 7771 (2019), 595–602.Google Scholar
- Jim Holmes, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. 2016. Extended high-temperature operation of silicon carbide CMOS circuits for Venus surface application. J. Microelectron. Electron. Packag. 13, 4 (2016), 143–154.Google ScholarCross Ref
- Mark Horowitz, Elad Alon, Dinesh Patil, Samuel Naffziger, Rajesh Kumar, and Kerry Bernstein. 2005. Scaling, power, and the future of CMOS. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’05). IEEE, 7–pp. Google ScholarDigital Library
- Shuoben Hou. 2019. Silicon Carbide High-temperature Photodetectors and Image Sensor. Ph.D. Dissertation. KTH Royal Institute of Technology.Google Scholar
- Chenming Hu. 2010. Modern Semiconductor Devices for Integrated Circuits. Vol. 2. Prentice Hall, Upper Saddle River, NJ.Google Scholar
- Xing Hu, Dylan Stow, and Yuan Xie. 2018. Die stacking is happening. IEEE Micro 38, 1 (2018), 22–28.Google ScholarCross Ref
- Yongjie Hu, Jie Xiang, Gengchiau Liang, Hao Yan, and Charles M. Lieber. 2008. Sub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed. Nano Lett. 8, 3 (2008), 925–930.Google ScholarCross Ref
- Stephen Hudgens and Brian Johnson. 2004. Overview of phase-change chalcogenide nonvolatile memory technology. MRS Bull. 29, 11 (2004), 829–832.Google ScholarCross Ref
- Clive Humby. 2006. Data is the new Oil. In Proceedings of the ANA Sr. Marketer’s Summit.Google Scholar
- Gary W. Hunter, Philip G. Neudeck, Robert S. Okojie, Glenn M. Beheim, J. A. Powell, and Liangyu Chen. 2003. An overview of high-temperature electronics and sensor development at NASA glenn research center. J. Turbomach. 125, 4 (2003), 658–664.Google ScholarCross Ref
- Rotem Ben Hur, Nimrod Wald, Nishil Talati, and Shahar Kvatinsky. 2017. SIMPLE MAGIC: Synthesis and in-memory mapping of logic execution for memristor-aided logic. In Proceedings of the 36th International Conference on Computer-Aided Design. IEEE Press, 225–232. Google ScholarDigital Library
- IEEE. 2018. International Roadmap for Devices and Systems Beyond CMOS. Technical Report.Google Scholar
- IEEE. 2018. International Roadmap for Devices and Systems Moore Moore. Technical Report.Google Scholar
- Intel. 2019. Intel Core i9-9900K Processor. Retrieved from https://www.intel.com/content/www/us/en/products/processors/core/i9-processors/i9-9900k.html.Google Scholar
- Adrian M. Ionescu and Heike Riel. 2011. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 7373 (2011), 329.Google Scholar
- Ahmad Ehteshamul Islam. 2013. Variability and reliability of single-walled carbon nanotube field effect transistors. Electronics 2, 4 (2013), 332–367.Google ScholarCross Ref
- Shubham Jain, Ashish Ranjan, Kaushik Roy, and Anand Raghunathan. 2017. Computing in Memory with Spin-transfer Torque Magnetic Ram. IEEE Trans. Very Large Scale Integr. Syst. 26, 3 (2017), 470–483. Google ScholarDigital Library
- Akhilesh Jaiswal and Kaushik Roy. 2016. Spin transfer torque memories for on-chip caches: Prospects and perspectives. In Proceedings of the 17th Latin-American Test Symposium (LATS’16). IEEE, 7–7.Google ScholarCross Ref
- Raj Jana, Gregory L. Snider, and Debdeep Jena. 2013. Sub-Boltzmann transistors with piezoelectric gate barriers. In Proceedings of the 3rd Berkeley Symposium on Energy Efficient Electronic Systems (E3S’13). IEEE, 1–2.Google ScholarCross Ref
- Matthew Jerry, Pai-Yu Chen, Jianchi Zhang, Pankaj Sharma, Kai Ni, Shimeng Yu, and Suman Datta. 2017. Ferroelectric FET analog synapse for acceleration of deep neural network training. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’17). IEEE, 6–2.Google ScholarCross Ref
- Javier Junquera and Philippe Ghosez. 2003. Critical thickness for ferroelectricity in perovskite ultrathin films. Nature 422, 6931 (2003), 506–509.Google Scholar
- Nam Sung Kim, Todd Austin, David Blaauw, Trevor Mudge, Jie S. Hu, Mary Jane Irwin, Mahmut Kandemir, Vijaykrishnan Narayanan et al. 2003. Leakage current: Moore’s law meets static power. Computer12 (2003), 68–75. Google ScholarDigital Library
- Daiki Kimoto. 2017. Characterization and Modeling of SiC Integrated Circuits for Harsh Environment. Ph.D. Dissertation. KTH Royal Institute of Technology.Google Scholar
- Kun Kong, Yun Shang, and Ruqian Lu. 2009. An optimized majority logic synthesis methodology for quantum-dot cellular automata. IEEE Trans. Nanotechnol. 9, 2 (2009), 170–183. Google ScholarDigital Library
- Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, and Hong Wang. 2018. Density tradeoffs of non-volatile memory as a replacement for SRAM-based last level cache. In Proceedings of the 45th Annual International Symposium on Computer Architecture. IEEE Press, 315–327. Google ScholarDigital Library
- Zoran Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. J. Kim, R. Sporer, C. Serrao et al. 2017. 14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’17). IEEE, 15–1.Google Scholar
- Emre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, and Suman Datta. 2012. Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores. In Proceedings of the 8th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. ACM, 245–254. Google ScholarDigital Library
- Shinichiro Kuroki, Hirofumi Nagatsuma, Milantha de Silva, Seiji Ishikawa, Tomonori Maeda, Hiroshi Sezaki, Takamaro Kikkawa, Takahiro Makino, Takeshi Ohshima, Mikael Östling et al. 2016. Characterization of 4H-SiC nMOSFETs in harsh environments, high-temperature and high gamma-ray radiation. In Materials Science Forum, Vol. 858. Trans Tech Publications, 864–867.Google Scholar
- Mark Lapedus. 2016. Mask maker worries grow. Retrieved November 3, 2019 from https://semiengineering.com/what-mask-makers-want/.Google Scholar
- Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting phase change memory as a scalable dram alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture. 2–13. Google ScholarDigital Library
- Gyu-hyeon Lee, Dongmoon Min, Ilkwon Byun, and Jangwoo Kim. 2019. Cryogenic computer architecture modeling with memory-side case studies. In Proceedings of the 46th International Symposium on Computer Architecture. 774–787. Google ScholarDigital Library
- H. Y. Lee, Y. S. Chen, P. S. Chen, P. Y. Gu, Y. Y. Hsu, S. M. Wang, W. H. Liu, C. H. Tsai, S. S. Sheu, P. C. Chiang et al. 2010. Evidence and solution of over-RESET problem for HfO x-based resistive memory with sub-ns switching speed and high endurance. In Proceedings of the International Electron Devices Meeting. IEEE, 19–7.Google Scholar
- Yoonmyung Lee, Daeyeon Kim, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, David Blaauw, and Dennis Sylvester. 2013. Low-power circuit analysis and design based on heterojunction tunneling transistors (HETTs). IEEE Trans. Very Large Scale Integr. Syst. 21, 9 (2013), 1632–1643. Google ScholarDigital Library
- David I. Lewin. 2002. DNA computing. Comput. Sci. Eng. 4, 3 (2002), 5–8. Google ScholarDigital Library
- Jing Li, Binquan Luan, and Chung Lam. 2012. Resistance drift in phase change memory. In Proceedings of the IEEE International Reliability Physics Symposium (IRPS’12). IEEE, 6C–1.Google ScholarCross Ref
- Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, and Yuan Xie. 2016. Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. In Proceedings of the 53rd Annual Design Automation Conference. ACM, 173. Google ScholarDigital Library
- Xiao Li and Hongwei Zhu. 2015. Two-dimensional MoS2: Properties, preparation, and applications. J. Mater. 1, 1 (2015), 33–44.Google Scholar
- Yang Li, Kui Yao, and Ganesh Shankar Samudra. 2016. Effect of ferroelectric damping on dynamic characteristics of negative capacitance ferroelectric MOSFET. IEEE Trans. Electron Devices 63, 9 (2016), 3636–3641.Google ScholarCross Ref
- Yu-Ming Lin, Joerg Appenzeller, Joachim Knoch, and Phaedon Avouris. 2005. High-performance carbon nanotube field-effect transistor with tunable polarities. IEEE Trans. Nanotechnol. 4, 5 (2005), 481–489. Google ScholarDigital Library
- Tz-yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang et al. 2013. A 130.7 2-layer 32-Gb ReRAM memory device in 24-nm technology. IEEE J. Solid-State Circ. 49, 1 (2013), 140–153.Google Scholar
- Yongpan Liu, Fang Su, Yixiong Yang, Zhibo Wang, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa et al. 2019. A 130-nm ferroelectric nonvolatile system-on-chip with direct peripheral restore architecture for transient computing system. IEEE J. Solid-State Circ. 54, 3 (2019), 885–895.Google ScholarCross Ref
- Juan Pablo Llinas, Andrew Fairbrother, Gabriela Borin Barin, Wu Shi, Kyunghoon Lee, Shuang Wu, Byung Yong Choi, Rohit Braganza, Jordan Lear, Nicholas Kau et al. 2017. Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons. Nature Commun. 8, 1 (2017), 1–6.Google ScholarCross Ref
- Gabriel H. Loh and Yuan Xie. 2010. 3D stacked microprocessor: Are we there yet?IEEE Micro 30, 3 (2010), 60–64. Google ScholarDigital Library
- Wei Lu and Charles M. Lieber. 2006. Semiconductor nanowires. J. Phys. D: Appl. Phys. 39, 21 (2006), R387.Google ScholarCross Ref
- Wei Lu, Jie Xiang, Brian P. Timko, Yue Wu, and Charles M. Lieber. 2005. One-dimensional hole gas in germanium/silicon nanowire heterostructures. Proc. Natl. Acad. Sci. U.S.A. 102, 29 (2005), 10046–10051.Google ScholarCross Ref
- Paul Malfy. 2018. Intel Core i9-9900K processor review. Retrieved November 3, 2019 from https://www.modders-inc.com/intel-core-i9-9900k-processor-review/6/.Google Scholar
- Pravin Mane, Nishil Talati, Ameya Riswadkar, Ramesh Raghu, and C. K. Ramesha. 2015. Stateful-NOR-based reconfigurable architecture for logic implementation. Microelectron. J. 46, 6 (2015), 551–562. Google ScholarDigital Library
- Thomas Mikolajick, Christine Dehm, Walter Hartner, Ivan Kasko, M. J. Kastner, Nicolas Nagel, Manfred Moert, and Carlos Mazure. 2001. FeRAM technology for high density applications. Microelectron. Reliabil. 41, 7 (2001), 947–950.Google ScholarCross Ref
- T. Mikolajick, U. Schroeder, and S. Slesazeck. 2020. The past, the present, and the future of ferroelectric memories. IEEE Trans. Electron. Dev. 67, 4 (2020), 1434–1443.Google ScholarCross Ref
- Dongmoon Min, Ilkwon Byun, Gyu-Hyeon Lee, Seongmin Na, and Jangwoo Kim. 2020. CryoCache: A fast, large, and cost-effective cache architecture for cryogenic computing. In Proceedings of the 25th International Conference on Architectural Support for Programming Languages and Operating Systems. 449–464. Google ScholarDigital Library
- Umesh K. Mishra, Primit Parikh, Yi-Feng Wu et al. 2002. AlGaN/GaN HEMTs-an overview of device operation and applications. Proc. IEEE 90, 6 (2002), 1022–1031.Google ScholarCross Ref
- Daniel Nagy, Guillermo Indalecio, Antonio J García-Loureiro, Muhammad A. Elmessary, Karol Kalna, and Natalia Seoane. 2018. FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability. IEEE J. Electron Dev. Soc. 6 (2018), 332–340.Google ScholarCross Ref
- Montassar Najari, Sebastien Fregonese, Cristell Maneux, Thomas Zimmer, Hassene Mnif, and N. Masmoudi. 2008. Towards compact modelling of Schottky barrier CNTFET. In Proceedings of the 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era. IEEE, 1–6.Google Scholar
- Philip G. Neudeck, Liangyu Chen, Roger D. Meredith, Dorothy Lukco, David J. Spry, Leah M. Nakley, and Gary W. Hunter. 2018. Operational testing of 4H-SiC JFET ICs for 60 days directly exposed to Venus surface atmospheric conditions. IEEE J. Electron. Dev. Soc. 7 (2018), 100–110.Google ScholarCross Ref
- Philip G. Neudeck, Steven L. Garverick, David J. Spry, Liang-Yu Chen, Glenn M. Beheim, Michael J. Krasowski, and Mehran Mehregany. 2009. Extreme temperature 6H-SiC JFET integrated circuit technology. Physica Status Solidi (a) 206, 10 (2009), 2329–2345.Google ScholarCross Ref
- Philip G. Neudeck, Roger D. Meredith, Liangyu Chen, David J. Spry, Leah M. Nakley, and Gary W. Hunter. 2016. Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions. AIP Adv. 6, 12 (2016), 125119.Google ScholarCross Ref
- Philip G. Neudeck, Robert S. Okojie, and Liang-Yu Chen. 2002. High-temperature electronics-a role for wide bandgap semiconductors?Proc. IEEE 90, 6 (2002), 1065–1076.Google ScholarCross Ref
- Philip G. Neudeck, David J. Spry, Liangyu Chen, Norman F. Prokop, and Michael J. Krasowski. 2017. Demonstration of 4H-SiC digital integrated circuits above 800 C. IEEE Electron. Dev. Lett. 38, 8 (2017), 1082–1085.Google ScholarCross Ref
- Philip G. Neudeck, David J. Spry, and Liang-Yu Chen. 2016. First-order SPICE modeling of extreme-temperature 4H-SiC JFET integrated circuits. Additional Papers and Presentations. HiTEC, 000263–000271.Google Scholar
- Kai Ni, Xunzhao Yin, Ann Franchesca Laguna, Siddharth Joshi, Stefan Dünkel, Martin Trentzsch, Johannes Müeller, Sven Beyer, Michael Niemier, Xiaobo Sharon Hu, et al. 2019. Ferroelectric ternary content-addressable memory for one-shot learning. Nature Electron. 2, 11 (2019), 521–529.Google ScholarCross Ref
- Y. Nosho, Y. Ohno, S. Kishimoto, and T. Mizutani. 2006. Relation between conduction property and work function of contact metal in carbon nanotube field-effect transistors. Nanotechnol. 17, 14 (2006), 3412.Google ScholarCross Ref
- Ugo Otuonye, Hee Woo Kim, and Wei D. Lu. 2017. Ge nanowire photodetector with high photoconductive gain epitaxially integrated on Si substrate. Appl. Phys. Lett. 110, 17 (2017), 173104.Google ScholarCross Ref
- Hongsik Park, Ali Afzali, Shu-Jen Han, George S. Tulevski, Aaron D. Franklin, Jerry Tersoff, James B. Hannon, and Wilfried Haensch. 2012. High-density integration of carbon nanotubes via chemical self-assembly. Nature Nanotechnol. 7, 12 (2012), 787.Google ScholarCross Ref
- Kyu-Sul Park, Sang-Jin Kim, In-Bok Baek, Won-Hee Lee, Jong-Seuk Kang, Yong-Bum Jo, Sang Don Lee, Chang-Keun Lee, Jung-Bum Choi, Jang-Han Kim et al. 2005. SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs. IEEE Trans. Nanotechnol. 4, 2 (2005), 242–248. Google ScholarDigital Library
- Eric Pop, David Mann, Qian Wang, Kenneth Goodson, and Hongjie Dai. 2006. Thermal conductance of an individual single-wall carbon nanotube above room temperature. Nano Lett. 6, 1 (2006), 96–100.Google ScholarCross Ref
- Kiran Puttaswamy and Gabriel H. Loh. 2006. Thermal analysis of a 3D die-stacked high-performance microprocessor. In Proceedings of the 16th ACM Great Lakes Symposium on VLSI. ACM, 19–24. Google ScholarDigital Library
- Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture. 24–33. Google ScholarDigital Library
- Branimir Radisavljevic, Aleksandra Radenovic, Jacopo Brivio, Valentina Giacometti, and Andras Kis. 2011. Single-layer MoS 2 transistors. Nature Nanotechnol. 6, 3 (2011), 147.Google ScholarCross Ref
- M. Radosavljević, St Heinze, J. Tersoff, and Ph Avouris. 2003. Drain voltage scaling in carbon nanotube transistors. Appl. Phys. Lett. 83, 12 (2003), 2435–2437.Google ScholarCross Ref
- Nagarajan Raghavan, Daniel D. Frey, Michel Bosman, and Kin Leong Pey. 2015. Statistics of retention failure in the low resistance state for hafnium oxide RRAM using a Kinetic Monte Carlo approach. Microelectron. Reliabil. 55, 9–10 (2015), 1422–1426.Google ScholarCross Ref
- D. Reinsel, J. Gantz, and J. Rydning. 2018. Data age 2025: The digitization of the world from edge to core. Retrieved from https://www. seagate. com/files/www-content/our-story/trends/files/idc-seagate-dataage-whitepaper. pdf.Google Scholar
- Bryan J. Rice, Vibhu Jindal, C. C. Lin, Jenah Harris-Jones, Harry Kwon, Andy Ma, Michael Goldstein, and Frank Goodwin. 2008. Overview of EUV Mask Metrology. Retrieved from https://www.nist.gov/system/files/documents/pml/div683/conference/Rice_2011.pdf.Google Scholar
- Seyed Mohammad Seyedzadeh, Rakan Maddah, Alex Jones, and Rami Melhem. 2016. Leveraging ecc to mitigate read disturbance, false reads and write faults in STT-RAM. In Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’16). IEEE, 215–226.Google ScholarCross Ref
- Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, and Vivek Srikumar. 2016. ISAAC: A convolutional neural network accelerator with in situ analog arithmetic in crossbars. ACM SIGARCH Comput. Architect. News 44, 3 (2016), 14–26. Google ScholarDigital Library
- Muhammad Shakir. 2019. Process Design Kit and High-temperature Digital ASICs in Silicon Carbide. Ph.D. Dissertation. KTH Royal Institute of Technology.Google Scholar
- Navin Shenoy. 2018. Intel’s 2018 Data-Centric Innovation Summit. Retrieved October 22, 2019 from https://s21.q4cdn.com/600692695/files/doc_presentations/2018/08/2018_08_DCIS_Shenoy_Final.pdf.Google Scholar
- Max M. Shulaker, Gage Hills, Rebecca S. Park, Roger T. Howe, Krishna Saraswat, H.-S. Philip Wong, and Subhasish Mitra. 2017. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 7661 (2017), 74.Google Scholar
- Max M. Shulaker, Gage Hills, Nishant Patil, Hai Wei, Hong-Yu Chen, H.-S. Philip Wong, and Subhasish Mitra. 2013. Carbon nanotube computer. Nature 501, 7468 (2013), 526.Google Scholar
- Benoît Sklénard, Philippe Blaise, Boubacar Traoré, Alberto Dragoni, Cécile Nail, and Elisa Vianello. 2017. Advances in the understanding of microscopic switching mechanisms in ReRAM devices. In Proceedings of the 47th European Solid-State Device Research Conference (ESSDERC’17). IEEE, 46–49.Google Scholar
- Young-Woo Son, Marvin L. Cohen, and Steven G. Louie. 2006. Energy gaps in graphene nanoribbons. Phys. Rev. Lett. 97, 21 (2006), 216803.Google ScholarCross Ref
- Linghao Song, Xuehai Qian, Hai Li, and Yiran Chen. 2017. Pipelayer: A pipelined reram-based accelerator for deep learning. In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA’17). IEEE, 541–552.Google ScholarCross Ref
- Ed Sperling. 2016. Multi-patterning issues at 7nm, 5nm. Retrieved November 3, 2019 from https://semiengineering.com/multi-patterning-problems-grow/.Google Scholar
- David J. Spry, Philip G. Neudeck, Dorothy Lukco, Liang Yu Chen, Michael J. Krasowski, Norman F. Prokop, Carl W. Chang, and Glenn M. Beheim. 2018. Prolonged 500°C operation of 100+ transistor silicon carbide integrated circuits. In Materials Science Forum, Vol. 924. Trans Tech Publications, 949–952.Google Scholar
- Y. Sugiyama, Y. Takeuchi, and M. Tacanot. 1992. Highly-sensitive InGaAs-2DEG Hall device made of pseudomorphic In0. 52A10. 48As/In0. 8Ga0. 2As heterostructure. Sensors Actuat. A: Phys. 34, 2 (1992), 131–136.Google ScholarCross Ref
- Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, and Suman Datta. 2013. Steep-slope devices: From dark to dim silicon. IEEE Micro 33, 5 (2013), 50–59. Google ScholarDigital Library
- Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, and Shahar Kvatinsky. 2018. Practical challenges in delivering the promises of real processing-in-memory machines. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’18). IEEE, 1628–1633.Google ScholarCross Ref
- Nishil Talati, Saransh Gupta, Pravin Mane, and Shahar Kvatinsky. 2016. Logic design within memristive memories using memristor-aided loGIC (MAGIC). IEEE Trans. Nanotechnol. 15, 4 (2016), 635–650.Google ScholarDigital Library
- Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, and Shahar Kvatinsky. 2019. CONCEPT: A column-oriented memory controller for efficient memory and PIM operations in RRAM. IEEE Micro 39, 1 (2019), 33–43.Google ScholarCross Ref
- Yuan Taur and Tak H. Ning. 2013. Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge, UK. Google ScholarDigital Library
- B. Turkot, S. Carson, and A. Lio. 2017. Continuing Moore’s law with EUV lithography. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’17. IEEE, 14–4.Google Scholar
- M. Vinet, P. Batude, C. Tabone, B. Previtali, C. LeRoyer, A. Pouydebasque, L. Clavelier, A. Valentian, O. Thomas, S. Michaud et al. 2011. 3D monolithic integration: Technological challenges and electrical results. Microelectron. Eng. 88, 4 (2011), 331–335. Google ScholarDigital Library
- Stefan Wachter, Dmitry K. Polyushkin, Ole Bethge, and Thomas Mueller. 2017. A microprocessor based on a two-dimensional semiconductor. Nature Commun. 8 (2017), 14948.Google ScholarCross Ref
- Han Wang, Lili Yu, Yi-Hsien Lee, Yumeng Shi, Allen Hsu, Matthew L. Chin, Lain-Jong Li, Madan Dubey, Jing Kong, and Tomas Palacios. 2012. Integrated circuits based on bilayer MoS2 transistors. Nano Lett. 12, 9 (2012), 4674–4680.Google ScholarCross Ref
- Wikichip. 2019. Wikichip, 4004—Intel. Retrieved from https://en.wikichip.org/wiki/intel/mcs-4/4004.Google Scholar
- Wikipedia. 2019. Wikipedia, The Free Encyclopedia. Retrieved from https://en.wikipedia.org/wiki/Instructions_per_second.Google Scholar
- Wikipedia. 2020. Wikipedia, The Free Encyclopedia. Retrieved from https://en.wikipedia.org/wiki/Ferroelectric_RAM.Google Scholar
- Wikipedia. 2020. Wikipedia, The Free Encyclopedia. Retrieved from https://en.wikipedia.org/wiki/Fe_FET.Google Scholar
- H.-S. Philip Wong and Deji Akinwande. 2011. Carbon Nanotube and Graphene Device Physics. Cambridge University Press.Google Scholar
- H.-S. Philip Wong, Simone Raoux, SangBum Kim, Jiale Liang, John P. Reifenberg, Bipin Rajendran, Mehdi Asheghi, and Kenneth E. Goodson. 2010. Phase change memory. Proc. IEEE 98, 12 (2010), 2201–2227.Google ScholarCross Ref
- Justin Wong and Sayeef Salahuddin. 2015. Piezoelectric Negative Capacitance. Ph.D. Dissertation. MA thesis. EECS Department, University of California, Berkeley.Google Scholar
- Jie Xiang, Wei Lu, Yongjie Hu, Yue Wu, Hao Yan, and Charles M. Lieber. 2006. Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nature 441, 7092 (2006), 489.Google ScholarCross Ref
- Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, and Yuan Xie. 2015. Overcoming the challenges of crossbar resistive memory architectures. In Proceedings of the IEEE 21st International Symposium on High Performance Computer Architecture (HPCA’15). IEEE, 476–488.Google ScholarCross Ref
- B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo, and D. L. Kwong. 2008. Vertical silicon-nanowire formation and gate-all-around MOSFET. IEEE Electron. Device Lett. 29, 7 (2008), 791–794.Google ScholarCross Ref
- Ran Yu, Yordan M. Georgiev, Samaresh Das, Richard G. Hobbs, Ian M. Povey, Nikolay Petkov, Maryam Shayesteh, Dan O’Connell, Justin D. Holmes, and Ray Duffy. 2014. Junctionless nanowire transistor fabricated with high mobility Ge channel. Rapid Res. Lett. 8, 1 (2014), 65–68.Google Scholar
- C.-M. Zetterling. 2013. Silicon carbide high-temperature electronics—Is this rocket science? Future Trends in Microelectronics: Frontiers and Innovations, Serge Luryi, Jimmy Xu, and Alex Zaslavsky (Eds.). John Wiley & Sons, 102–109.Google Scholar
- Zhen Zhang and John T. Yates Jr. 2012. Band bending in semiconductors: Chemical and physical consequences at surfaces and interfaces. Chem. Rev. 112, 10 (2012), 5520–5551.Google ScholarCross Ref
- Ping Zhou, Bo Zhao, Jun Yang, and Youtao Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. ACM SIGARCH Comput. Architect. News 37, 3 (2009), 14–23. Google ScholarDigital Library
- Mohammed A. Zidan, John Paul Strachan, and Wei D. Lu. 2018. The future of electronics based on memristive systems. Nature Electron. 1, 1 (2018), 22.Google ScholarCross Ref
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- A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors
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