Hot-carrier-induced device degradation in Schottky barrier ambipolar polysilicon transistor
Introduction
The architecture of a Schottky barrier (SB) transistor essentially reduces the parasitic resistances of the source and drain regions, inducing an abrupt junction interface. Hence, SB MOSFETs have been extensively studied as a promising candidate for the next generation of CMOS devices [1], [2], [3], [4]. Although several methodologies have been suggested to enhance the device performance, SB MOSFETs exhibit high bias off-state current, high subthreshold swing, and low ON/OFF current ratio owing to the difficulty in modulating the Schottky barrier height [5], [6], [7], [8]. However, instead of exploring alternative candidates for the next generation of CMOS devices, studies have been focusing on applying the SB MOSFET architecture to reconfigurable field-effect transistors (RFETs), the novel functional devices implementing n- and p-channel FET characteristics, using SB MOSFET devices [9], [10], [11], [12], [13]. The device characteristics of an ambipolar SB MOSFET can switch from n-channel to p-channel operational behaviors by changing the gate biases, making it suitable for RFETs. To implement multi-functional integrated circuits using RFETs, the device structures blocking the undesired charge carrier polarity with an electrostatic gate were studied to reduce the large off-state current [5], [6], [7], [8]. Additionally, ambipolar SB transistors were employed to implement multilevel SB nanowire SONOS memory by utilizing the large off-state current [14].
In ambipolar SB transistors, the gate bias directly controls the potential barrier height and width at the Schottky interface by injecting predominant carriers to the source or drain electrodes. To achieve a symmetrical complementary operation, the gate biases require equal concentrations of electrons and holes to be injected into the channel. Therefore, the Schottky barrier height controlling the carrier injection into the channel must be identical for both source and drain electrodes. Crystalline and polycrystalline silicon thin-film transistors with a mid-band-gap Ni-silicide (NiSi) Schottky barrier have been studied as promising devices for nanowire CMOS and RFETs [15], [16], [17]. As NiSi demonstrates similar barrier heights for electrons (0.6–0.65 eV) and holes (0.45–0.5 eV), low growth temperature, and low lattice mismatch of 4% with silicon, it is widely used in nano-scale SB MOSFETs [18], [19]. Although the charge transport in the SB MOSFET is determined by the thermionic emission and tunneling components, the current drive is dominantly governed by the Fowler-Nordheim tunneling component above the threshold regime, because the barrier heights of NiSi for the electron and hole are much larger than the thermal energy (kBT).
When an ambipolar SB transistor switches from n-channel to p-channel operation by changing the gate biases, the device can be degraded due to the both injection of hot electrons and hot holes. As the hot-carrier-induced trap charges at the gate oxide modify the Schottky barrier height and width, the device performance of the ambipolar SB MOSFET can be degraded after hot-carrier stress. The threshold voltage (VTH) of the n-channel FET increased and the VTH of the p-channel FET decreased negatively after hot-carrier stress, owing to the negative and positive charges trapped in the gate oxide, respectively. A few studies on the device degradation of SB MOSFETs under hot-carrier stress, including our work, reported that the charges trapped in the gate oxide modified the SB barrier shape, deteriorating the device performance [20], [21]. Remarkably, a study reported that some of the hot electrons generated at the source electrode in SB transistors were injected into the gate electrode and trapped in the gate oxide near the source edge [22]. Thus, differential negative conductance was observed in the IDS versus VDS characteristics. Thus far, there are no experimental studies conducted on the hot-carrier-induced device degradation in ambipolar transistors, despite these transistors being the most promising devices for RFETs.
In this study, we investigated the device degradation in SB ambipolar polysilicon transistors using electron or hole trapped charges in the gate oxide near the source edge during hot-carrier stress. We explained the device degradation mechanism using the hot-carrier generation at the source electrode, and validated it by monitoring and measuring the gate currents and transfer characteristics in the forward and reverse modes before and after hot-carrier stress, respectively.
Section snippets
Device fabrication
Ambipolar SB polysilicon thin-film transistors were fabricated on glass substrates as shown in Fig. 1. A 160-nm-thick amorphous silicon film was deposited using plasma-enhanced chemical vapor deposition at a temperature of 300 °C to form an active layer. The crystallization of deposited amorphous silicon films was performed using a XeCl excimer laser at a wavelength of 308 nm. The energy density for excimer laser annealing (ELA) was optimized at 400 mJ/cm2 for a 10-μm overlap rate and 100-Hz
Results and discussion
Fig. 2 presents the n-channel and p-channel transfer characteristics of an ambipolar SB-MOSFET with a channel length (L) and width (W) of 8 μm and 20 μm, respectively. The transfer curves reveal that the fabricated device can switch from n-channel to p-channel operational behaviors by changing the gate bias. The transfer characteristics were measured for VDS values of + 1 V and − 1 V. The maximum field effect of the electron mobility of 18.2 cm2/V∙s and VTH of 3.8 V at VDS = 1 V, and hole
Conclusion
We observed that the behavior of hot-carrier-induced device degradation in SB ambipolar transistors was different from that of the unipolar MOSFETs. After hot-electron stress, the drain current in the p-channel operation decreased, while it increased in the n-channel operation. In contrast, after hot-hole stress, the drain current in the p-channel operation increased, while it decreased in the n-channel operation. This can be explained by the hot-carrier generation at the source electrode in
Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgement
This work was supported by the Incheon National University Research Grant in 2020.
Jong-Tae Park received the B.S. degree in electronics engineering from Kyungpook National University, Korea, in 1981, and the M.S. and Ph.D. degrees from Yonsei University, Korea, in 1983 and 1987, respectively, where he performed the device characterization and modeling of SOI CMOS. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon,
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Jong-Tae Park received the B.S. degree in electronics engineering from Kyungpook National University, Korea, in 1981, and the M.S. and Ph.D. degrees from Yonsei University, Korea, in 1983 and 1987, respectively, where he performed the device characterization and modeling of SOI CMOS. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and oxide semiconductor thin film transistor.