Abstract
Crosstalk fault on the chip wires seriously jeopardizes data reliability. One of the most effective methods to reduce crosstalk fault is crosstalk fault avoidance coding (CAC) based on numeral systems. CAC methods reduce crosstalk fault by preventing certain transitions from occurring. Improved One-Lambda Coding (IOLC) demonstrates the best performance among all types of CAC methods since it shows the least delay and area occupancy overhead. However, designers of larger-width buses need a systematic framework for generating cost-effective Improved One-Lambda Codes (IOLC). Such a framework should have two distinctive features: Firstly, it should specify the number of code words in each particular width, which is referred to as cardinality. Secondly, it should provide an algorithm for producing complete and unambiguous numeral systems. In this paper, the following items have been provided to achieve these two features. 1) A recursive formula called recursive symmetry has been proposed to determine the extent of cardinality for Improved One-Lambda Coding. 2) Using the recursive symmetry formula, an algorithm has been developed to generate different numeral systems for Improved One-Lambda Coding. The evaluation results showed that sending code words through the Improved One-Lambda Coding method using our proposed algorithm improves the status of delay in the worst cases
Similar content being viewed by others
Abbreviations
- CAC:
-
Crosstalk Avoidance Code
- FTC:
-
Forbidden Transition Code
- FOC:
-
Forbidden Overlap Code
- FPC:
-
Forbidden Pattern Code
- OLC:
-
One-Lambda Code
- IOLC:
-
Improved One-Lambda Code
- SOTA:
-
Same and Opposite Transition Avoidance
- ITRS:
-
International Technology Roadmap for Semiconductors
References
Frantz AP, Kastensmidt FL, Carro L, Cota E (2006) Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk. Proc Int Test Conf (ITC), pp.1–9
Lin SMPDJ, Zhu S, Liu X, Huang X, Huang X, Yan M, Yu Z (2017) A Scalable Network-on-Chip Microprocessor with 2.5D Integrated Memory and Accelerator. In IEEE Trans Circuits Syst I: Regul Pap 64(6):1432–1443
International Technology Roadmap for Semiconductors (2000) July 2000. http://www.itrs2.net
Duan C, LaMeres BJ, Khatri SP (2010) On and Off-Chip Crosstalk Avoidance in VLSI Design, Springer
Murali S, Theocharides T, Vijaykrishnan N, Irwin MJ, Benini L, De Micheli G (2005) Analysis of Error Recovery Schemes for Networks on Chip. IEEE Des Test Comput 22(5):434–442
Sridhara SR, Shanbhag NR (2007) Coding for Reliable on-chip Buses: a Class of Fundamental Bounds and Practical Codes. IEEE Trans Comput Aided Des Integr Circuits Syst 26(1):977–982
Benini L, De Micheli G (2002) Networks on Chips: a New SoC Paradigm. IEEE Trans Comput 35(1):70–78
Lakshmi KASS, Keerthi A, Sri KM, Vinodhini M (2020) Code with Crosstalk Avoidance and Error Correction for Network on Chip Interconnects. Proc. 2020 4th Int Conf Trends Electron Inform (ICOEI)(48184), pp. 75–79
Ghoneima M, Ismail IY, Khellah MM, Tschanz WJ (2006) Reducing the Effective Coupling Capacitance in Buses using Threshold Voltage Adjustment Techniques. IEEE Trans Circuits Syst I Fundam Theory Appl 53(9):1928–2193
Shi F (2015) Signal Processing Techniques and Applications. Ph.D. Thesis, Lehigh University, USA
Duan C, Tirumala A, Khatri SP (2001) Analysis and Avoidance of Cross-talk in on-chip Buses. Proc Hot Interconnects pp. 133–138
Mahdavi Z, Shirmohammadi Z, Miremadi SG (2016) ACM: Accurate crosstalk modeling to predict channel delay in Network-on-Chips. 2016 IEEE 22nd Int Symp On-Line Test Robust Syst Des (IOLTS), pp. 7–8
Bai X, Dey S (2001) High-Level Crosstalk Defect Simulation for System-on-Chip Interconnects. Proc. 19th IEEE VLSI (Very Large Scale Integration) Test Symp pp. 169–175
Agarwal L, Sylvester K, Blaauw D (2006) Modeling and Analysis of Crosstalk Noise in Coupled RLC Interconnects. IEEE Trans Comput Aided Des Integr Circuits Syst 25(9):892–901
Fu B, Ampadu P (2011) Error Control for Network-on-Chip Links. Springer Sci Business Media
Chang CS, Cheng J, Huang TK, Lee DS, Chen CY (2016) Coding Rate Analysis of Forbidden Overlap Codes in High-Speed Buses. ACM Trans Model Perform Eval Comput Syst 1(2):8
Wu X, Yan Z (2010) Efficient Codec Designs for Crosstalk Avoidance Codes Based on Numeral Systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(4):548–558
Chang CS, Cheng J, Huang TK, Huang XC, Lee DS, Chen CY (2015) Bit-Stuffing Algorithms for Crosstalk Avoidance in High-Speed Switching. IEEE Trans Comput 64(12):3404–3416
Shirmohammadi Z (2019) OP-Fibo: An efficient Forbidden Pattern Free CAC design 65:104–109
Shirmohammadi Z, Miremadi SG (2016) On Designing an Efficient Numerical-based Forbidden Pattern Free Crosstalk Avoidance Codec for Reliable Data Transfer of NoCs. Microelectron Reliab 63:304–313
Shirmohammadi Z, Mozafari F, Miremadi SG (2017) An Efficient Numerical-based Crosstalk Avoidance Codec Design for NoCs. Microprocess Microsyst (MICPRO) 50:127–137
Shirmohammadi Z, Mahdavi Z (2018) An Efficient and Low Power One-Lambda Crosstalk Avoidance Code Design for Network on Chips. Microprocess Microsyst (MICPRO) 63:36–45
Duan C, Calle VHC, Khatri SP (2009) Efficient on-chip Crosstalk Avoidance Codec Design. IEEE Trans Very Large Scale Integr (VLSI) Syst 17(4):551–560
Subramaniam B, Muthusamy S, Gengavel GJJoAI, Computing H (2020) Crosstalk minimization in network on chip (NoC) links with dual binary weighted code CODEC. Ambient Intell Humaniz Comput pp. 1–6
Patooghy A, Torkaman MF, Elahi M (2019) Your Hardware is All Wired Up! Attacking Network-On-Chips via Crosstalk Channel. Proc. the 12th Int Workshop Netw Chip Architectures pp. 7
Shi F, Wu X, Yan Z (2012) New crosstalk avoidance codes based on a novel pattern classification. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(10):1892–1902
Tehranipour MH, Ahmed N, Nourani M (2003) Testing SoC Interconnects for Signal Integrity using Boundary Scan. Proc. VLSI (Very Large Scale Integration) Test Symp (VTS) pp.158–172
Zimmer H, Jantsch A (2003) A Fault Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-chip. Proc. Hardware/Software Codesign Syst Synth (ISSS/CODES), pp. 188–193
Zhang J, Friedman GE (2004) Effect of Shield Insertion on Reducing Crosstalk Noise between Coupled Interconnects. Proc. Int Symp Circuits Syst (ISCAS), pp. 529–53
Shirmohammadi Z, Taali M, Sabzi HZ (2019) InduM: An Accurate probablity Inductance-based Model to Predict Delay in Chips. 2019 9th Int Conf Comput Knowl Eng (ICCKE), pp. 414–419
Acknowledgments
The authors would like to thank any comment and suggestion of reviewers on this article. The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.
Author information
Authors and Affiliations
Contributions
Z. Shirmohammadi and M. Taali collected the data and designed the experiments. Z. Shirmohammadi carried out the data analysis. Z. Shirmohammadi and M. Taali interpreted the results and wrote the manuscript.
Corresponding author
Ethics declarations
Conflict of Interest
The author declares that there is no conflict of interests regarding the publication of this manuscript. In addition, the ethical issues, including plagiarism, informed consent, misconduct, data fabrication and/or falsification, double publication and/or submission, and redundancy have been completely observed by the authors.
Additional information
Responsible Editor V. Champac.
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Taali, M., Shirmohammadi, Z. A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula. J Electron Test 37, 395–408 (2021). https://doi.org/10.1007/s10836-021-05950-4
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-021-05950-4