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Compensation of power quality problems through DSTATCOM using various phase locked loops

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Abstract

The control algorithm of a DSTATCOM majorly influences its function. The key role of a phase locked loop (PLL) as a fundamental extractor in the control algorithm is inevitable. It is used to extract the information of the fundamental like phase angle, frequency and amplitude from the distorted voltage/current signal. According to the information collected, the performance of the control algorithm of the DSTATCOM is judged for various conditions like unbalanced and distorted harmonic condition. This paper presents the study of three PLLs, namely unified three-phase signal processor PLL (UTSP), multi-sequence harmonic decoupling PLL (MSHDC) and harmonic/inter-harmonic DC offset (HIHDO) PLL. An unconstrained optimization problem has been formulated with DC and AC bus voltage errors. The gains of proportional integral controller are projected using RAO algorithm. It is an algorithm specific type and parameter less. The DSTATCOM is able to compensate the reactive power and mitigate the grid current harmonics which are caused due to a nonlinear load through an optimized PI controller for the considered PLL the control algorithms. An analysis of performance using simulation results, dynamic response and complexity in computation has been made for the PLLs considered. The fast recovery during dynamic conditions of the system has opted HIHDO PLL as better one among the other two proposed PLLs. The laboratory performance of the considered system for HIHDO PLL using d-SPACE has been provided.

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Funding

Under Science and Engineering Research Board-New Delhi Project (Extra Mural Research Funding Scheme), Grant No. SB/S3/EECE/030/2016, DATED 17/08/2016.

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Authors and Affiliations

  1. Department of Electrical Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, 395007, India

    Sabha Raj Arya, Rakesh Maurya & Jayadeep Srikakolapu

  2. Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram, Chennai, 600127, India

    B. Chitti Babu

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  1. Sabha Raj Arya
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  2. Rakesh Maurya
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  3. Jayadeep Srikakolapu
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  4. B. Chitti Babu
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Correspondence to Sabha Raj Arya.

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Appendices

Appendix 1

1.1 Parameters for simulation work

400 V 50 Hz Three-phase AC supply, 0.06 Ω source resistance, 1mH source inductance, an AC voltage controller type nonlinear load (R = 10 Ω and L = 2mH and R = 45 Ω and L = 2mH during unbalance in one phase) DC bus voltage 700 V, 10 micro sec of sampling time, Interfacing inductance (Lf) = 2.25 mH, switching frequency (fs) = 5 kHz, cut-off frequency of low-pass filter = 10 Hz.

Appendix 2

2.1 Parameters for test work

AC mains: 3-phase, 230 V (line) with distortion, 50 Hz; nonlinear-type load: AC voltage controller with restive load (R = 21 Ω and R = 45 Ω during unbalance in ‘A’ phase) ohm; passive filter parameter (ripple filter): Rf = 5 Ω, Cf = 20μF; sampling time (Ts) = 40 μs, DC bus voltage = 400 V; DC bus capacitor (Cdc) = 4500 μF; interfacing inductor: Lf = 4 mH, DC bus cut-off frequency of low-pass filter = 10 Hz.

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Arya, S.R., Maurya, R., Srikakolapu, J. et al. Compensation of power quality problems through DSTATCOM using various phase locked loops. Electr Eng 104, 45–66 (2022). https://doi.org/10.1007/s00202-021-01341-2

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